Reed—Muller码的双向搜索译码

本文提出了Ｒｅｅｄ－Ｍｕｌｌｅｒ码的一种双向搜索算法，并证明了该算法实现了广义最小距离译码。其复杂度较Ｆｏｒｎｅｙ的译码算法降低很多，而其完备译码的性能经计算机模拟表明，与最大似然译码几乎一样。     

用Spartan^TM—II FPGA实现Reed—Solomon编码／译码方案

本文简述Ｒｅｅｄ－Ｓｏｌｏｍｏｎ纠错理论及用Ｘｉｌｉｎｘ－Ｓｐａｒｔａｎ＾ＴＭ－ＩＩ系列ＦＰＧＡ实现Ｒｅｅｄ－Ｓｏｌｏｍｏｎ编码／译码方案。     

Turbo码软判决输出维特比译码方案的改进

Turbo码是一种新的纠错编码,具有十分强的纠错能力。Turbo码编码端采用两个或两个以上的卷积并行级联构成,译码端则采用以基于软判决信息输入/输出的反馈迭代译码结构。译码算法是Turbo码设计的核心,现已有的两种主要的译码算法——MAP和SOVA。SOVA是一种改进的维特比算法,使其可以逐比特输出与MAP算法类似的软判决信息。该文综述了Turbo码SOVA译码的几种改进方式,并分析了这几种改进方式及仿真结果。     

一种改进的大数逻辑译码算法

大数逻辑译码算法的突出优点是实现非常简单,但其纠错能力不强。该文提出了一种改进方法,除利用接收矢量中正确码元提供的信息外,还利用了错误码元提供的信息。改进算法遵循码字错误概率最小和码元错误概率最小两种最佳译码准则,实现了最小距离译码。理论分析和仿真结果均表明改进算法可有效提高纠错能力。     

Turbo码软判决输出维特比译码方案的改造

Turbo码是一种新的纠错编码，具有十分强的纠错能力。Turbo码编码端采用两个或两个以上的卷积并行级联构成，译码端则采用以基于软判决信息输入／输出的反馈迭代译码结构。译码算法是Turbo码设计的核心，现已有的两种主要的译码算法——MAP和SOVA。SOVA是一种改进的维特比算法，使其可以逐比特输出与MAP算法类似的软判决信息。该文综述了Turbo码SOVA译码的几种改进方式，并分析了这几种改进方式及仿真结果。     

Turbo码软判决输出维持比译码方案的改进

Turbo码是一种新的纠错编码，具有十分强的纠错能力，Turbo码编码端采用两个或两个以上的卷积并行级联构成，译码端则采用以基于软判决信息输入/输出的反馈迭代译码结构。译码算法是Turbo码设计的核心，现巳有的两种主要的译码算法-MAP和SOVA。SOVA是一种改进的维持比算法，使其可以逐比特输出与MAP算法类似的软判决信息。该文综述了Turbo码SOVA译码的几种改进方式，并分析了这几种改进方式及仿真结果。     

引入行重参数的改进不规则LDPC码译码算法

低密度奇偶校验(LDPC)码是一种逼近香农极限 的线性分组码,而好的非规则LDPC 码其性能优于同码率的规则码。在非规则LDPC码的对数似然比置信传播(LLR-BP)译码算 法中,由于行重大小的不同,校验节点对伪后验判决贡献的外部信息不同,为此提出一种基 于行重的改进LLR-BP译码算法,该算法引入行权重系数,用以调整不同行重外部信息的作 用,提高了系统的译码性能。仿真结果表明:在低信噪比时,改进的LLR-BP译码算法对译 码性能与标准的LLR-BP译码算法的性能几乎相同;在中高信噪比时,改进的LLR-BP译码 算法的误码性能优于LLR-BP译码算法,在码长为64,误码率是10－5时,改进LLR- BP译码算法较之传统LLR-BP译码算法的编码增益提高了0.15 dB。     

适用于磁盘阵列的纠双错码分析

比较分析了三种适用于盘阵列的纠双错码：二维奇偶校验（２Ｄ），Ｒｅｅｄ－Ｓｏｌｏｍｏｎ（ＲＳ）码以及ＥＶＥＮＯＤＤ码的编码，译码复杂度及其相应小写性能．２Ｄ码编码简单，但构成阵列“性能／价格”差．ＲＳ和ＥＶＥＮＯＤＤ码为最优冗余编码，ＲＳ码编，译码较ＥＶＥＮＯＤＤ码复杂，但小写性能比ＥＶＥＮＯＤＤ编写好。     

Reed-Muller码的大数逻辑译码及其与Viterbi算法的比较

文章首先介绍了Reed-Muller码的发展历史,以及构造其生成矩阵的特殊方法,从而对Reed-Muller进行编码。其次,重点讨论了Reed-Muller码的大数逻辑译码,这是一种适用于Reed-Muller码的简单又有效的译码方法,并举例进行了详细地阐述。Viterbi算法广泛应用于分组码、卷积码的译码,考虑到它的最优译码特性,文章运用Viterbi算法对ReedMuller码进行译码,将其性能与大数逻辑译码进行比较。由于Reed-Muller码的网格图比较复杂,文章提出一种方法,通过将线性分组码的生成矩阵转换成面向网格的形式,减少了网格图的状态数,从而降低了Viterbi译码的复杂性。     

DVB-S2标准IRA-LDPC译码算法研究与改进

首先对DVB-S2标准LDPC码编码原理、IRA码以及校验矩阵的特征进行了分析,接着对该标准中LDPC码的Tanner图参数进行了总结,然后对不同的译码算法从性能和复杂度方面进行了比较,并且对不同迭代次数时LDPC码的判决信息的分布进行了分析,最后对各种译码算法的性能和复杂度进行了总结.仿真结果表明,SPA译码算法性能最优但是复杂度最大,MinSum算法的复杂度最低但是性能最差,而改进的MinSum算法则在复杂度和性能方面是前面两种算法的折中,对实际工程的应用有较强的借鉴作用.     

TD—LTE系统Reed—Muller译码的仿真及FPGA实现

主要基于FPGA实现TD—LTE系统中的Reed—Muller译码,包括Reed—Muller译码的介绍、方案的构成、FPGA实现流程、以及实现结果分析。并在Virtex-6芯片上,进行了仿真、综合、板级验证。实现结果表明,该Reed—Muller译码算法应用到TD—LTE射频一致性测试仪表中具有良好的高效性和可靠性。     

3GPP中的Reed-Muller编译码算法

3GPP的物理层协议中对传输格式组合指示TFCI采用了类Reed_-Muller编码,但没有具体解释其编码方法和译码算法,本文详细讨论了其编译码方法,比较了两种快速哈达马变换和经典一阶Reed_-Muller码的译码算法,并指出3GPP协议设计中的成功和不足之处,同时通过仿真测试验证了其纠错能力.     

32位CRC校验码的并行算法及硬件实现

通过对CRC校验码原理的分析,研究了一种并行32位CRC算法。该算法采用递推的方法,直接得出计算多位数据后的CRC余数与计算前余数之间的逻辑关系。相对于一般的按位串行计算或者查表并行计算的方法来说,该方法运算速度快且不需要额外的空间存储余数表,十分有利于硬件实现。     

Soft IP Compiler for a Reed‐Solomon Decoder

In this paper, we present a soft IP compiler for the Reed‐Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed‐Solomon decoder with appropriate sub‐architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.     

低时延RS-CC级联码的设计与实现

为提高手持无线电台的纠错和时延特性,考虑设计一种短码长RS-CC级联码.通过对Reed-Solomon码缩短和截断以及对卷积码删余,提出了一种低时延的级联码设计方案,并进行性能分析和软硬件实现.结果表明,在高斯信道下,当Eb/No达到4.2 dB时,能够实现10-4的误码率性能.设计的RS-CC级联码码长较短,编解码固有时延低,译码速度提升30％,适合低时延应用.     

Maximum-likelihood decoding of Reed-Solomon codes is NP-hard

Maximum-likelihood decoding is one of the central algorithmic problems in coding theory. It has been known for over 25 years that maximum-likelihood decoding of general linear codes is NP-hard. Nevertheless, it was so far unknown whether maximum-likelihood decoding remains hard for any specific family of codes with nontrivial algebraic structure. In this paper, we prove that maximum-likelihood decoding is NP-hard for the family of Reed-Solomon codes. We moreover show that maximum-likelihood decoding of Reed-Solomon codes remains hard even with unlimited preprocessing, thereby strengthening a result of Bruck and Naor.     

A dual protection scheme for impulsive noise suppression in OFDM systems

Orthogonal frequency division multiplexing (OFDM) can be susceptible to impulsive noise arising from numerous sources in a noisy communications environment. Conventional Reed–Solomon (RS) codes are particularly useful for burst-error corrections and have been employed in OFDM systems to manage impulsive noise. The performance gains, however, have been somewhat limited given the sensitivity to other noise types typically present in a noisy channel. In this regard, a novel scheme utilizing a time-domain pre-processing mean filter in combination with RS coding is proposed for impulsive noise suppression in OFDM systems. This scheme is split into two stages. In the first stage, a proposed mean filter effectively detects and removes the impulsive noise using the measured statistics of the impulsive noise. In contrast to a conventional blanking type filter, the traditional mean replacement value is replaced by a composite comparison value (CCV). This principle creates a more accurate estimate of the original OFDM signal after impulsive noise removal. The residual impulsive noise is then managed by a RS decoder in the second stage. Our results show that this dual faceted approach improves OFDM performance when compared to filtering and coding techniques alone.     

VLSI implementation of Reed-Solomon encoder algorithm for communication systems

Reed Solomon codes are used to identify and correct data errors in transmission and storage systems. In this paper we designed a compact RS(255, 223) encoder structure based on analysis of the Reed-Solomon (RS) coding theory used in deep space communications. The encoder is implemented with 32 optimized finite multipliers, of which the redundant operations are reduced to minimize the number of modulo 2 additions or XOR gates based on analyzing the structure of multipliers in RS encoder that are simple and can ensure high speed operations. The simulation results show that the designed structure has advantages such as high efficiency and low complexity ensuring good coding performance.     

RS码译码器综述

ＲＳ码是差错控制领域中一类重要的线性分组码，由于具有很强的纠随机错和突发错的能力，被广泛应用于各种差错控制系统中，本文从ＲＳ译码算法，ＲＳ译码器的ＶＬＳＩ结构和ＲＳ码系统性能三方面论述了ＲＳ译码器的发展现状，并展望了译码器的未来发展方向。     

Single carrier digital terrestrial television broadcasting

A transmission system for digital terrestrial television broadcasting has been designed. This system is based on the European cable system but uses stronger error correction and better equalization. The stronger error correction is a concatenation of Reed Solomon coding RS [204,188,17] and convolutional coding with R_conv=1/2, 2/3, 3/4, 5/6 and 7/8. The algorithm which is used for convolutional decoding is the Viterbi algorithm. To provide the Viterbi decoder with soft decision information, every symbol bit will be expanded with two soft decision (reliability) bits. The modulation scheme of the terrestrial transmission system is 64-QAM square root raised cosine filtered with a roll off factor α=0.15. The mapping of the symbols into the 64-QAM constellation is a Gray-mapping over the complete I,Q-plane. In this paper the performances of the terrestrial transmission system are simulated and analyzed