高动态多进制扩频信号的载波跟踪技术研究

针对高动态环境下多进制扩频信号的载波同步问题,在分析锁相环(PLL)和锁频环(FLL)环路各自优点的基础上,研究了采用锁频环和锁相环相结合的方式进行载波信号跟踪。利用FLL动态适应能力较强和PLL具有较好跟踪精度的特点,实现动态信号的快速、精确跟踪。理论分析和仿真结果表明,该方法具有良好的跟踪效果。     

基于ISCP-DPSK调制的直接序列扩频技术

使用符号内连续相位差分相移键控(ISCP-DPSK)调制的直接序列扩频方法可以在实现扩频抗干扰的同时保留ISCP-DPSK调制信号的准恒包络特性和优良的频谱特性,有利于非线性和功率受限的应用场合。由于采用非相干的信号解扩解调方法,避免了低信噪比下的载波和相位估计与跟踪,简化了系统设计。计算机仿真表明,基于ISCP-DPSK调制的直接序列扩频能有效对抗本振偏离、多普勒频移等引起的符号间相位变化影响,8倍扩频和16倍扩频的增益仅与理论值分别相差0.1 dB和0.2 dB。     

采用PL2101在低压电力线上实现数据通信

介绍了在低压电力线上实现数据通信的扩频载波芯片PL2101，以及采用PL2101构成的电力线扩频载波通信系统。     

一个新的扩频通信系统

多载波与扩频技术相结合，形成多载波扩频技术，现在已成为移动通信领域的研究热点。多载波扩频技术主要有两类，一类是频域扩频，另一类是时域扩频。本文提出将时域扩频与频域扩频相结合的多载波扩频系统方案，并进行了系统性能分析。     

一种降低MC-CDMA信号峰值平均功率比的方法

多载波信号的峰值平均功率比远远大于单载波系统,而且峰平比随着子载波个数无限增长.本文采用格雷互补序列及它的一个子类S-R序列作为多载波CDMA（MC-CDMA）的扩频码,来降低它的输出峰值平均功率比,对于任意长度的扩频码其峰平比不超过6dB.对长度为32的S-R序列扩频、Hadamard扩频及长度为31的m序列扩频的MC-CDMA信号进行了比较,其峰平比分别为6dB,13.68dB和12dB.     

一种降低OFDM系统PAPR的内插子载波选择性映射方案

为了降低OFDM系统的高峰值功率比(PAPR),提出了一种基于DFT扩频内插子载波选择性映射的OFDM传输方案。根据DFT扩频特有的降低PAPR特性,以及子载波映射对PAPR的重要影响,提出一种可选择的映射方式应用到DFT扩频系统中。通过搭建仿真系统得出,基于DFT扩频的选择性映射内插子载波OFDM系统的PAPR比传统OFDM系统的PAPR低0.5~2dB,系统Q值比常规DFT扩频OFDM系统高1,是一种降低OFDM系统PAPR的理想设计方案。     

一种面向水下移动通信的组合差分扩频水声通信方法

针对水下移动平台(AUVs)直接序列扩频(DSSS)水声通信过程中大多普勒时变带来的频偏及载波相位跳变问题,该文提出一种组合差分扩频通信方法。该方法设计一种2维组合差分(TCD)扩频帧结构,接收端通过对重复码时域加窗相关实现时变多普勒粗估计;接收端提出一种频率压缩-能量接收器(FC-ED),通过采用能量检测接收器提高接收端处理多普勒容限,使用频率压缩法多频点压缩处理进一步提高系统鲁棒性,实现扩频码识别映射解码;最后提出一种组合差分算法,实现2维组合扩频间的极性差分解码,在能量接收映射解码基础上引入极性调制,进一步提高频谱利用率。经理论及仿真试验分析,该方法具备一定的抗时变多普勒能力,在恒加速度相对运动–8 dB信噪比条件下误码率小于10–2。     

码分多址(CDMA)扩频系统载波提取电路的设计

本文根据码分多址(CDMA)扩频系统的特点,提出了一种切实可行的载波提取电路的设计方法。这种方法具有通用性,易于采用中小规模集成电路实现。     

一种新的扩频通信系统

多载波与扩频技术相结合,形成多载波扩频技术,现在已成为移动通信领域的研究热点.多载波扩频技术主要有两类,一类是频域扩频,另一类是时域扩频.本文提出将时域扩频与频域扩频相结合的多载波扩频系统方案,并进行了系统性能分析.     

跳频扩频系统的Matlab模拟仿真实现

跳频扩频技术采用特定的扩频函数及载波跳变来实现频谱展宽,具有很强的抗干扰性,并具有信息隐蔽、多址保密通信的特点;PSK调制方式由基带脉冲控制载波相位。在Matlab／Simulink下建立了采用BPSK方式的跳频扩频（FH—SS）通信系统模拟模型,并编程仿真实现该系统,对跳频扩频通信的实现有重要意义。     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².     

Bandpass Sigma–Delta Modulator Employing SAW Resonator as Loop Filter

Continuous-time bandpass (BP) sigma-delta modulators (SigmaDeltaMs) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with G_m-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP SigmaDeltaMs are demonstrated in a 0.35-mum CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution     

宽带低相噪频率综合器设计与实现

为满足某雷达信号设计要求,文中基于国产小数锁相环芯片GM4704产生7.12～9.12 GHz的信号,采用传统的PLL方式产生,低相位噪声、低杂散的频率综合器。同时,给出了设计过程并对相关的设计参数进行分析,应用相关的PLL仿真软件对环路滤波器进行仿真设计,通过实际电路测试,相位噪声达到-97 dBc/Hz@1 kHz与理论计算较接近,杂散达到-70 dB。     

An adaptive PLL tuning system architecture combining high spectralpurity and fast settling time

An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The relationship of performance aspects (settling time, phase noise, and spurious signals) to design variables (loop bandwidth, phase margin, and loop filter attenuation at the reference frequency) are presented, and the basic tradeoffs of the new concept are discussed. A circuit implementation of the adaptive PLL, optimized for use in a multiband (global) car-radio tuner IC, is described in detail. The realized tuning system achieved state-of-the-art settling time and spectral purity performance in its class (integer-N PLLs): a signal-to-noise ratio of 65 dB, a 100-kHz spurious reference breakthrough signal under -81 dBc, and a residual settling error of 3 kHz after 1 ms, for a 20-MHz frequency step. It simultaneously fulfills the speed requirements for inaudible frequency hopping and the heavy signal-to-noise ratio specification of 64 dB     

二端网络声表面波滤波器电磁仿真分析及设计

为了模拟高频低损耗声表面波(SAW)滤波器的设计,该文采用二端口阻抗元2T结构建立了包含外壳及点焊线电磁响应的数学模型,并利用回路电流分析法,推导出该模型下的Y、S参数。且在该模型基础上用Matlab编写了程序,为某电台设计了一款频率为1 561 MHz,-1 dB带宽大于30 MHz,插入损耗小于2 dB,带外抑制大于40 dB的SAW滤波器,理论模拟与实测吻合较好,表明了此模型在设计高频低损耗SAW滤波器的可行性。     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.     

C波段锁相变频器模块

设计了一种采用锁相环技术的C波段变频器模块,其原理是输入的信号与压控振荡器(VCO)信号相混频,产生两个信号频率差的信号,这个信号与差频信号IF进行鉴频鉴相,产生的误差信号经环路滤波送入压控振荡器(VCO)的调谐端完成锁相,这时压控振荡器输出的信号就是需要的信号。采用这种技术,模块输出的有用信号与输入信号泄漏到输出端口的功率比在83dB以上,可以达到较好的效果,同时可有效避免使用体积较大的腔体带通滤波器。     

A new PLL frequency synthesizer with high switching speed

A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10²~10³ times higher than conventional PLL synthesizers, and spurs of less than -60 dB     

星座组网中直扩信号快速同步改进算法

基于直扩体制的时分多址(TDMA)卫星星座组网,信号帧前导段长度越短、净荷长度越长,数据传输的效率就越高.但是,直扩体制信号帧前导段长度越短意味着接收信号捕获增益就越低,捕获概率就越低.另外,前导段长度越短要求锁相环信号跟踪收敛速度越快.星座组网整网数据传输效率受到卫星信号同步算法性能的制约.为了提高直扩信号同步算法的性能,从捕获与跟踪两个部分对同步算法进行了改进,提出了一种直扩信号快速同步改进算法.针对捕获部分,分析了前置低通滤波器带宽对扩频信号的自相关函数的影响,通过选择滤波器参数在保证相关主峰无明显恶化情况下提升1/4码片偏差相关峰能量1 dB以上.针对跟踪部分,提出了一种调整闭环控制系统的零极点分布优化锁相环时域响应的锁相环设计方法,给出了基于控制理论优化锁相环闭环系统的零极点分布的四点原则,利用该方法设计的锁相环能大大降低信号跟踪的收敛时间.仿真结果表明,所提改进算法与传统同步方法相比能有效提高信号的捕获概率,加快信号跟踪的收敛速度,明显减少信号的同步时间.     

一种自偏置锁相环电路的分析与测试

自偏置锁相环电路结构自提出以来便受到了极大的关注,人们普遍认为其可以改善锁相环的相位噪声。为了验证这种结构能否改善传统锁相环电路的相位噪声性能,根据锁相环的基本理论设计并实现了一种可进行重新配置的锁相环电路结构,电路中的锁相环结构可以在传统锁相环、自偏置锁相环和普通偏置锁相环之间进行切换。使用信号源分析仪分别测试得到了这3种结构的相位噪声性能：自偏置锁相环的带内相位噪声比普通锁相环恶化了约6 dB,而采用普通偏置锁相环使环路等效分频比减小5的相位噪声比普通锁相环改善了约14 dB。理论与测试结果均表明,自偏置锁相环和普通锁相环相比,环路反馈回路中的分频比并没有有效降低,因此自偏置锁相环的相位噪声性能并没有得到改善。