单层多晶的EEPROM

针对传统双层多晶EEPROM的诸多不足之处,介绍了相对较有潜力的单层多晶的EEPROM,主要对比了传统的双层多晶的EEPROM和单层多晶的EEPROM(single poly EEPROM),展示了single poly EEPROM的应用前景,同时提出了single poly EEPROM所面临的问题,并有针对性地给出了几种解决方案.     

单层多晶的EEPROM

针对传统双层多晶EEPROM的诸多不足之处，介绍了相对较有潜力的单层多晶的EEP-ROM，主要对比了传统的双层多晶的EEPROM和单层多晶的EEPROM(single poly EEPROM)，展示了single poly EEPROM的应用前景，同时提出了single poly EEPROM所面临的问题，并有针对性地给出了几种解决方案。     

基于TCAD软件的单层多晶EEPROM器件模拟分析

利用TCAD软件对单层多晶EEPROM器件特性进行了模拟分析,介绍了单层多晶EEPROM存储单元结构与原理的基础,针对TCAD软件中模拟分析单层多晶EEPROM器件特性时存在的困难,提出了一种两个MOS管外加电阻的等效模型来替代单层多晶EEPROM存储单元结构进行等效模拟.通过编程模拟了单层多晶EEPROM器件性能,模拟分析得到的特性曲线与理论曲线能较好吻合,验证了等效模型方案的可行性.     

一种应用于可编程模拟电路的EEPROM单元

为改善传统EEPROM在可编程模拟电路应用中的不足,提出了一种新型的单层多晶EEPROM单元结构,与常见的单层多晶EEPROM结构相比,该结构采用双N阱、附加栅结构实现,与标准数字CMOS工艺兼容,具有写入电流控制准确、阈值电压低的特点.通过对器件的分析及仿真,验证了该结构在模拟电路应用中的有效性.     

一种用于模拟电路修调的EEPROM电路

介绍了一种用在模拟电路中修调的EEPROM电路.该电路采用一种新型的单层多晶EEPROM结构,与传统的双栅EEPROM结构相比,该结构与数字CMOS工艺兼容,成本低、成品率高.使用在一个基准电压电路中时,其基准电压的调节范围达到±4.82%,调节精度达到4mV.EEPROM修调电路可广泛应用于各种高精度需求的电路中.     

EEPROM失效机理初探

在分析了双层多晶硅FLOTOXEEPROM各种失效模式后，从理论上提出了提高EEPROM可靠性的各种措施。提高隧道氧化层和多晶硅之间氧化层的质量，减小擦／写电压和擦／写时间，减小隧道氧化层的面积，都是提高EEPROM可靠性的有效措施。     

一种用于模拟电路测试与修调的方法

针对模拟电路中一些基准量的测试与修调,本文提出了一种通过管脚复用技术和单多晶的EEPROM相结合的方法对模拟电路中的基准电压进行了测试与修调,然后通过仿真验证了该方法实现的电路功能。     

不同钝化结构的HgCdTe光伏探测器暗电流机制

在同一HgCdTe晶片上制备了单层ZnS钝化和双层（CdTe+ZnS）钝化的两种光伏探测器,对器件的性能进行了测试,发现双层钝化的器件具有较好的性能．通过理论计算,分析了器件的暗电流机制,发现单层钝化具有较高的表面隧道电流．通过高分辨X射线衍射中的倒易点阵技术研究了单双层钝化对HgCdTe外延层晶格完整性的影响,发现单层ZnS钝化的HgCdTe外延层产生了大量缺陷,而这些缺陷正是单层钝化器件具有较高表面隧道电流的原因．     

不同钝化结构的HgCdTe光伏探测器暗电流机制

在同一HgCdTe晶片上制备了单层ZnS钝化和双层(CdTe+ZnS)钝化的两种光伏探测器,对器件的性能进行了测试,发现双层钝化的器件具有较好的性能.通过理论计算,分析了器件的暗电流机制,发现单层钝化具有较高的表面隧道电流.通过高分辨X射线衍射中的倒易点阵技术研究了单双层钝化对HgCdTe外延层晶格完整性的影响,发现单层ZnS钝化的HgCdTe外延层产生了大量缺陷,而这些缺陷正是单层钝化器件具有较高表面隧道电流的原因.     

双层螺旋RF MEMS电感的模拟与设计

分析了双层螺旋电感的等效电路模型,研究了一种与传统CMOS工艺兼容的MEMS工艺,通过腐蚀电感结构下的硅衬底使电感悬空.利用HFSS软件对一些双层螺旋微电感进行了模拟,模拟结果表明,相比传统单层电感,双层电感可以减少60%的芯片面积,10nH的电感也只需要很小的面积,经过MEMS后处理的双层螺旋电感的最大Q值都超过了20.     

A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon

Oxides thermally grown from polycrystalline silicon are known to conduct much higher currents than oxides grown on monocrystalline material, which has led to their application in floating-gate electrically erasable programmable READ-only memories (EEPROM) devices (so-called textured devices) for the purpose of electrical programming and erasing of the memory device. This increased conductivity has been previously explained qualitatively by field enhancement due to the surface roughness of the polysilicon-polyoxide interfaces, but a quantitative model that could explain and predict the true injection current behavior was never proposed. In this paper, a new model is introduced, which is able to explain all of the experimental observations of conduction in polyoxides, including trapping phenomena. The new model is verified by comparison with two types of capacitor measurements. Since electron trapping in the oxide is included in the model it can also be used to investigate the degradation behavior of the textured-type floating-gate EEPROM cells. In all cases it is found that the nonuniformity of the polyoxide current strongly influences its behavior and that more specifically for EEPROM devices this nonuniformity puts severe limits on the number of program ERASE cycles that are possible.     

Novel single-poly EEPROM with damascene control-gate structure

A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al/sub 2/O/sub 3/ grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al/sub 2/O/sub 3/, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-/spl kappa/ material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.     

New M6805 Microcomputers Aim at Automotive Applications

Several new additions to the MC6805 family of microcomputers include features particularly suited for automotive electronics. These devices feature application specific logic for automotive ignition systems and instrumentation designs. The MC6805S2, MC680S3, and MC68705S3 microcomputers are useful for engine ignition controls, where asynchronous events, such as engine speed and spark dwell time must be computed with high accuracy. The MC6805K2 microcomputer features EEPROM for critical data retention when the power source is disconnected. The instrumentation odometer is one such application where the EEPROM feature is mandatory. The MC68HC05C4 (ROM version) and M68HC805C4 (EEPROM version) are the latest general purpose MCU's that also offer many important features for automotive applications. The HCMOS silicon technology allows minimal power dissipation which means the devices can operate in an ambient temperature range of -55 to +125 degrees C. These two devices also feature SCI and SPI serial interface ports. The devices run at a fast 2.1-MHz internal bus speed.     

A 512-kb flash EEPROM embedded in a 32-b microcontroller

A 512-kb flash EEPROM developed for microcontroller applications is reported. Many process and performance constraints associated with the conventional flash EEPROM have been eliminated through the development of a new flash EEPROM cell and new circuit techniques. Design of the 512-kb flash EEPROM, which is programmable for different array sizes, has been evaluated from 256- and 384-kb arrays embedded in new 32-b microcontrollers. The 512-kb flash EEPROM has incorporated the newly developed source-coupled split-gate (SCSG) flash EEPROM cell, Zener-diode controlled programming voltages, internally generated erase voltage, and a new differential sense amplifier. It has eliminated overerase and program disturb problems without relying on tight process controls and on critical operational sequences and timings, such as intelligent erase, intelligent program, and preprogram before erase. A modular approach was used for chip design to minimize development time and for processing technology to achieve high manufacturability and flexibility     

A single poly EEPROM cell structure for use in standard CMOSprocesses

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits     

Deposited inter-polysilicon dielectrics for nonvolatile memories

Deposited instead of thermally grown oxides were studied to form very high-quality inter-polysilicon dielectric layers for embedded nonvolatile memory application. It was found that by optimizing the microstructure, i.e., texture and morphology of the polysilicon layers, and by optimizing the post dielectric deposition anneal, very high-quality dielectric layers can be obtained. In this paper it is shown on simple capacitor structure level and full EEPROM device level that the electrical properties of interpoly dielectric layers can be improved tremendously by using deposited dielectric layers with additional rapid thermal anneal. Typical results are: a high charge-to-breakdown (Q_BD≈25 C/cm²), low leakage currents and decreased charge trapping during constant current stress. An additional advantage is the low thermal budget, which is very attractive for embedded applications. However, results depend on the polysilicon preparation, dielectric type and RTP anneal environment. From electrical evaluation it appeared that even for deposited dielectric layers the influence of polysilicon surface roughness and corners is considerable. The optimized combination of flat polysilicon layers, deposited inter-polysilicon dielectric and additional optimized rapid thermal anneal have been applied in full EEPROM devices. Cycling over one million cycles was possible, which indicates an endurance improvement by a factor of 10     

Breakdown voltage characteristics of thin oxides and their correlation to defects in the oxide as observed by the EBIC technique

Thin oxides are widely used as the tunneling dielectric in floating gate EEPROM devices and as gate dielectric in short-channel MOS devices. The oxides are required to have high breakdown voltage and low defect density for reliable operation of the devices. With the Electron Beam Induced Current (EBIC) technique, defects in the oxide which lead to lower values of the oxide breakdown voltage have been observed.     

EEPROM单元辐射机理研究

随着EEPROM存储器件在太空和军事领域的广泛应用,国际上对EEPROM抗辐射性能的研究越来越多。为了满足太空及军事领域的需要,文章分别研究了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,比较了FLOTOX和SONOS单元抗辐射性能的优劣,得出由于FLOTOX单元受工艺和结构的限制,抗辐射性能不如SONOS单元。同时在做抗辐射加固设计时,FLOTOX单元还需要考虑到电压耦合比的问题,且不利于等比例缩小。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM制作提供了理论基础。     

SONOS结构EEPROM单元辐射效应分析

随着EEPROM存储器件在太空和军事领域的广泛应用,对EEPROM抗辐射性能的研究越来越多。为了满足应用的需要,文章比较了FLOTOX和SONOS两种EEPROM工艺制成的存储单元在辐射条件下所受的影响,分析了FLOTOX和SONOS单元抗辐射性能的优劣,得出:SONOS结构的EEPROM单元,其抗辐射性能优于FLOTOX结构。并分析了在辐射条件下,SONOS结构受辐射影响的数学模型。文章的研究不但满足了目前的工作需要,还为以后抗辐射EEPROM研究提供了理论基础。