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1.
In this paper we evaluate several routing protocols for mobile, wireless, ad hoc networks via packetlevel simulations. The ad hoc networks are multihop wireless networks with dynamically changing network connectivity owing to mobility. The protocol suite includes several routing protocols specifically designed for ad hoc routing, as well as more traditional protocols, such as link state and distance vector, used for dynamic networks. Performance is evaluated with respect to fraction of packets delivered, endtoend delay, and routing load for a given traffic and mobility model. Both small (30 nodes) and medium sized (60 nodes) networks are used. It is observed that the new generation of ondemand routing protocols use much lower routing load, especially with small number of peertopeer conversations. However, the traditional link state and distance vector protocols provide, in general, better packet delivery and endtoend delay performance.  相似文献   

2.
A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma–delta analog-to-digital converter and a second-order sinc type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8–512 depending of the PN code length. The circuit was implemented in 0.8 m CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 m×686 m and the current drain is approximately 370 A.  相似文献   

3.
Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 m and 1.2 m BiCMOS processes.  相似文献   

4.
A fully integrated multi-stage symmetrical structure chargepump and its application to a multi-value voltage-to-voltage converterfor on-chip EEPROM programming are presented. The multi-valuevoltage-to-voltage converter is designed to offer two output voltages,power supply and triple power supply alternatively, which is neededfor a memory array. A dynamic analysis of the multi-stage symmetricalstructure charge pump and an optimization design in terms of circuitarea are also given. The circuit is implemented in a 1.2 CMOSprocess and the measurement results show that a voltage pulse as shortas 5 s with a rise time of 3 s is obtained. For a 5 V powersupply and with a resistive charge of 100 k, the programmingoutput voltage can reach as high as 11 V and output current forprogramming is over 110 A, which are high enough to program thememory cell.  相似文献   

5.
We present a mixed-mode VLSI chip performing unsupervised clustering and classification, implementing models of Fuzzy Adaptive Resonance Theory (ART) and Learning Vector Quantization (LVQ), and extending to variants such as Kohonen Self-Organizing Maps (SOM). The parallel processor classifies analog vectorial data into a digital code in a single clock, and implements on-line learning of the analog templates, stored locally and dynamically using the same adaptive circuits for on-chip quantization and refresh. The unit cell performing fuzzy choice and vigilance functions, adaptive resonance learning and long-term analog storage, measures 43 m×43 m in 1.2 m CMOS technology. Experimental learning results from a fabricated 8-input, 16-category prototype are included.  相似文献   

6.
This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of –163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 s were achieved. The IC was implemented by using 0.35-m CMOS process. It takes 860 m×620 m of total chip area and consumes 17.6 mA with a 3.0 V power supply.  相似文献   

7.
A new methodology to develop variable gain amplifiers is developed. The methodology is based on a feedback loop to generate the exponential characteristic, which is required for VGA circuits. The proposed idea is very suitable for applications that require very low power consumption, and as an application, a new current mode variable gain amplifier will be shown. The gain is adapted via a current signal ranges from –7.5 A to +6.5 A. Pspice simulations based on Mietec 0.5 m CMOS technology show that the gain can be varied over a range of 29.5 dB, with bandwidth of 3 MHz at maximum gain value. The circuit operates between ±1.5 V and consumes an average amount of power less than 495 W.  相似文献   

8.
This paper describes the design and implementation of a transmit/receive switch for 2.4 GHz ISM band applications. The T/R switch is implemented in a 0.35 m bulk CMOS process and it occupies 150 m · 170 m of die area. A parasitic MOSFET model including bulk resistance is used to optimize the physical dimensions of the transistors with regard to insertion loss and isolation. The measured insertion loss is 1.3 dB without port matching. Simulations using measured s-parameters indicate that an insertion loss of 0.8 dB can be obtained with a conjugate match. The measured isolation is 42 dB and the maximum transmit power is 16 dBm.  相似文献   

9.
A readout circuit for a 640 × 480 pixels FPA (focal plane array) has been successfully designed, fabricated and tested. The circuit solution is based on a per pixel source-follower direct injection (SFDI) pre-amplifier. Signal multiplexing is performed in both X and Y direction. The pixel size is 25 m × 25m. The chip is optimized for a QWIP (quantum well infrared photodetector) operating at a temperature of 70 K. The circuit has been realized in a standard 0.8 m CMOS process.  相似文献   

10.
This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.  相似文献   

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