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量子全加器构造的探讨 总被引:1,自引:0,他引:1
本文探讨了由Toffoli门和受控非门等量子逻辑门构成低位输入、低位输出的量子全加器的电路,并分析了该种量子全加器的变换操作。通过比较推导出有多位输入、多位输出量子全加器的电路组合规律. 相似文献
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全加器是算术运算的基本单元,设计结构简单的全加器有利于缩小数字自理芯片的面积。根据最新的XOR门结构设计了一种新的全加器,这种结构的一位全加器只用20只MOS管,对这种新的全加器,用PSPICE进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。 相似文献
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全加器实现的基本原理是基于进位传播和进位产生的PG逻辑。根据现有的PG逻辑计算公式,本文推导出一种新的等价型逻辑表达式,并验证了其正确性。将该等价型逻辑表达式用于全加器的设计中,能够改变原有的全加器结构,并改变布线通道的连线数目和连线方式。 相似文献
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介绍了一种基于0.7μm磷化铟(InP)双异质结双极型晶体管(DHBT)工艺的超高速全加器,将加法运算与数据同步锁存融合设计来提高计算速度,采用多数决定运算法则设计单层晶体管并联型进位电路来降低功耗。测试结果表明,全加器的最高时钟频率达32.2 GHz,包含锁存器的全加器整体电路功耗为350 mW。 相似文献
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低功耗非全摆幅互补传输管加法器 总被引:1,自引:1,他引:1
文章提出了一种新型传输管全加器,该全加器采用互补传输管逻辑(Complementary Pass-Transistor Logic)实现.与现有的CPL全加器相比:该全加器具有面积、进位速度和功耗上的优势:并且提供了进位传播信号的输出,可以更简单的构成旁路进位加法器(Carry SkipAdder).在此全加器基础上可以实现一种新型行波进位加法器(Ripple Carry Adder),其内部进位信号处于非全摆幅状态,具有高速低功耗的特点.HSPICE模拟表明:对4位加法器而言,其速度接近CMOS提前进位加法器(Carry Look ahead Adder),而功耗减小了61%.适用于高性能、低功耗的VLSI电路设计. 相似文献
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作为一种新型的纳米器件,量子元胞自动机(Quantum-dot cellular automata,QCA)有望取代传统CMOS器件.本文总结了目前已提出的三种全加器(Full Adder,FA)架构,通过概率转移矩阵(Probabilistic Transfer Matrix,PTM)分析找出其中最稳定的架构,进一步地,利用这三种全加器分别构建串行加法器,并从复杂度、不可逆功耗、成本等方面进行比较,结果发现性能最优的全加器架构为MR Azghadi FA.随后,选择该架构提出了一种针对全加器的新型逻辑门和共面QCA全加器电路,并应用此全加器设计了多位串行加法器,经对比分析表明,本文所提出的全加器电路在面积、元胞数和功耗等方面均有较大改进,且具有很好的扩展性. 相似文献
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为有效消除密码器件在执行算法时以能量消耗方式泄漏密码信息,本文通过对灵敏放大型逻辑和差分能量攻击原理的研究,采用多电源和多阈值电压(Muti-Supply Muti-V th ,MSMV)CMOS电路技术设计一种具有低功耗和抗差分能量攻击性能的逻辑电路,实现对输出负载低摆幅充放电.依此进一步提出一种新型全加器结构,从而可以以低摆幅的方式对双轨电路进行编码.HSPICE模拟验证表明,所设计的全加器逻辑功能正确,抗差分能量攻击性能明显.与传统基于SABL逻辑的全加器比较,该结构具有显著的低功耗特性. 相似文献
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Mahdiar Ghadiry Mahdieh Nadi Abu Khari A’Ain 《Circuits, Systems, and Signal Processing》2013,32(1):1-14
This paper presents a new 8-bit adder circuit, called discrepant low PDP 8-bit adder (DLPA) based on three new full adder cells, which have been designed based on requirements of different positions in each 8-bit adder circuit. In order to design the full adder cells, a new and general method has been proposed aiming to achieve full-swing output and low number of transistors. The proposed adder along with several state-of-the-art adders from the literature have been extensively analyzed and compared together. The results revealed that the power-delay product of DLPA is almost more than 20 % less than that of other compared circuits. 相似文献
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Lin J.-F. Hwang Y.-T. Sheu M.-H. Ho C.-C. 《IEEE transactions on circuits and systems. I, Regular papers》2007,54(5):1050-1059
In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases 相似文献
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Venkata Rao Tirumalasetty Madhusudhan Reddy Machupalli 《International Journal of Electronics》2019,106(4):521-536
This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS. 相似文献
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This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster. 相似文献
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This paper presents a novel design of a high performance full adder cell based on carbon nanotube field-effect transistors (CNTFET). This full adder cell has been designed to be used in ripple carry adder (RCA) optimally so that carry-propagation delay decreases without increase in hardware costs. High speed in RCA structure, the low number of transistors and simplicity in design are the main advantages of the proposed design in comparison with the previous works. Moreover, to increase the proposed RCA speed, carry-propagation chain has been reduced to six cells using only 14 transistors per 4 bits in the worst case, regardless of the adder width. The simulation results using HSPICE demonstrate that a significant improvement in delay, power and power-delay product compared with the state-of-the-art works can be achieved. The results in different temperatures, supply voltages, frequencies and load capacitors have also been obtained. 相似文献
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Yingtao Jiang Al-Sheraidah A. Yuke Wang Sha E. Jin-Gyun Chung 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2004,51(7):345-348
The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster. 相似文献
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加法运算是数字系统中最基本的算术运算.为了能更好地利用加法器实现减法、乘法、除法、码制转换等运算,提出用Multisim虚拟仿真软件中的逻辑转换仪、字信号发生器、逻辑分析仪,时全加器进行功能仿真设计、转换、测试、分析,强化Multisim的使用,并通过用集成全加器74LS283实现两个一位8421码十进制数的减法运算,... 相似文献
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In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8?V, 75°C demonstrate power reduction by 59.4% in case of 1?bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1?bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45?V applied in active mode improves the maximum operating frequency by 16% in case of 1?bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode. 相似文献