Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours

Analog Switches (AS) play an essential role in a large number of Mixed-Signal circuits. Depending on the use of AS, designers have optimised their topology to meet the needs of each specific switching function. Furthermore, the success of Field Programmable devices in the digital domain (FPGAs) has motivated some manufacturers to explore similar solutions to fast prototype in the Analog and Mixed Signal domains. In this work, we explore the defective behaviours of programmable AS under realistic catastrophic and parametric defects. A classification of the DC defective behaviours for bridging and open defects is presented. This classification shows that the simple fault model with faulty state of permanently transistor stuck-on or stuck-off is not sufficient to reflect the real behaviour of a defective switch. It has also been found that parametric defects such as threshold voltage variations are not DC testable, and would therefore require additional AC tests.     

The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain

This article introduces ATR's CAM-Brain Machine (CBM), an FPGA based piece of hardware which implements a genetic algorithm (GA) to evolve a cellular automata (CA) based neural network circuit module, of approximately 1,000 neurons, in about a second, i.e. a complete run of a GA, with 10,000 s of circuit growths and performance evaluations. Up to 65,000 of these modules, each of which is evolved with a humanly specified function, can be downloaded into a large RAM space, and interconnected according to humanly specified artificial brain architectures. This RAM, containing an artificial brain with up to 75 million neurons, is then updated by the CBM at a rate of 130 billion CA cells per second. Such speeds should enable real time control of robots and hopefully the birth of a new research field that we call brain building. The first such artificial brain, to be built by ATR starting in 2000, will be used to control the behaviors of a life sized robot kitten called Robokoneko.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

Simulation‐based performance evaluation of routing protocols for mobile ad hoc networks

In this paper we evaluate several routing protocols for mobile, wireless, ad hoc networks via packetlevel simulations. The ad hoc networks are multihop wireless networks with dynamically changing network connectivity owing to mobility. The protocol suite includes several routing protocols specifically designed for ad hoc routing, as well as more traditional protocols, such as link state and distance vector, used for dynamic networks. Performance is evaluated with respect to fraction of packets delivered, endtoend delay, and routing load for a given traffic and mobility model. Both small (30 nodes) and medium sized (60 nodes) networks are used. It is observed that the new generation of ondemand routing protocols use much lower routing load, especially with small number of peertopeer conversations. However, the traditional link state and distance vector protocols provide, in general, better packet delivery and endtoend delay performance.     

Dynamic capacity allocation and hybrid multiplexing techniques for ATM wireless LANs

We consider digital wireless multimedia LANs and timevarying traffic rates. To deal effectively with the dynamics of the timevarying traffic rates, a Traffic Monitoring Algorithm (TMA) is deployed to dynamically allocate channel capacities to the heterogeneous traffics. The TMA is implemented as a higher level protocol that dictates the capacity boundaries within two distinct framed transmission techniques: a Framed Time DomainBased (FTDB) technique and a Framed CDMA (FCDMA) technique. The performance of the TMA in the presence of the FTDB technique is compared to its performance in the presence of the FCDMA technique for some traffic scenarios. The performance metrics used for the TMAFTDB and TMAFCDMA combinations are channel capacity utilization factors, traffic rejection rates, and traffic delays. It is found that the TMAFTDB is superior to the TMAFCDMA when the speed of the transmission links is relatively low and the lengths of the transmitted messages are relatively short. As the speed of the transmission links and the length of the transmitted messages increase, the TMAFCDMA eventually outperforms the TMAFTDB.     

Performance and implementation of clustered‐OFDM for wireless communications

An elegant means by which highspeed burst wireless transmission can be accomplished with small amounts of overhead is through a novel technique referred to as clusteredOFDM (Cimini et al., 1996). By using OFDM modulation with a long symbol interval, clusteredOFDM overcomes the complex and costly equalization requirements associated with single carrier systems. Moreover, the need for highly linear power amplifiers typically required in OFDM systems is alleviated through the use of multiple transmit antennas combined with nonlinear coding. The clustering technique also leads to a natural implementation of transmit diversity. This paper reports on preliminary results on the performance of a clusteredOFDM system as well as the design and implementation of a clusteredOFDM transmitter. The prototype transmitter can deliver 7.5 Mbps, and it is expected that this data rate could be easily tripled with existing technology in a second generation system. The paper also describes the architectural tradeoffs made in order to reduce the hardware complexity of the boards as well as some experimental results showing the operation of the transmitter.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

Consistency management in Deno

We describe a new replicatedobject protocol designed for use in mobile and weaklyconnected environments. The protocol differs from previous protocols in combining epidemic information propagation with voting, and in using fixed perobject currencies for voting. The advantage of epidemic protocols is that data movement only requires pairwise communication. Hence, there is no need for a majority quorum to be available and simultaneously connected at any single time. The protocols increase availability by using voting, rather than primarycopy or primarycommit schemes. Finally, the use of perobject currencies allows voting to take place in an entirely decentralized fashion, without any server having complete knowledge of group membership. We show that currency allocation can be used to implement diverse policies. For example, uniform currency distributions emulate traditional voting schemes, while allocating all currency to a single server emulates a primarycopy scheme. We present simulation results showing both schemes, as well as the performance advantages of using currency proxies to temporarily reallocate currency during planned disconnections. Furthermore, we discuss an initial design of the underlying replicatedobject system and present a basic API.