Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.     

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of these transient IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient IR voltage drops can exceed 20% for a 20 power line.     

Bounds on the sizes of irredundant test sets and sequences for combinational logic networks

We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks. The networks are composed of AND, OR, NAND, NOR, and XOR gates. The fault model assumes that single stuck-at-zero faults occur on the lines of the networks, with the additional requirement that XOR gates be tested with all possible input combinations. The goal is to provide a simple and efficient implementation that processes the fanout-free subnetworks separately, and then combines the results without the need to consider the effects of reconvergent fanout. We introduce the concepts of irredundant test sets, where no test can be deleted regardless of the order of test application, and irredundant test sequences, where every test detects at least one additional fault when tests are applied in order. Identifying and differentiating between these types of collections of tests allows us to understand more precisely the mechanisms and expected performance of test generation and test compaction methods. We apply our test counting technique and two other published procedures to a set of benchmark circuits. Our bounds are shown to compare favorably to the results obtained by the other published approaches. We obtain minimal and maximal test sets and test sequences using a greedy optimization technique. Our bounds are shown to produce tight bounds for the smaller circuits; they grow more conservative as the size of the circuits increase.     

An Analog Self-Test Based on Differential I DD Monitoring Supported by Differential I OUT Checking

This paper proposes a novel DFT scheme that combines two test techniques—differential power supply current (I _DD ) monitoring and differential output current (I _OUT ) checking—in a single analog self-test. The DFT scheme is aimed at fully differential analog circuits. Fault detection is provided by means of differential measurement of the on-chip parameters, such as the I _DD and I _OUT currents. Due to the differential nature of the test principle used, no reference measurement is required prior to the test, thus the fault detection exhibits a significantly reduced dependency on process parameter variations, variation of temperature during the test as well as outside interference's. Based on measurement results, the realistic tolerance band for fault detection was determined and the fault coverage, resulting from previous simulation experiments, was adjusted.     

New Delay-Time Measurements on a 64-kb Josephson–CMOS Hybrid Memory With a 600-ps Access Time

A 64-kb subnanosecond Josephson–CMOS hybrid random-access memory (RAM) has been developed with ultrafast hybrid interface circuits. The hybrid memory is designed and fabricated using a commercial 0.18- $muhbox{m}$ CMOS process and NEC-SRL's 2.5- $hbox{kA/cm}^{2}$ Nb process for Josephson circuits. The millivolt-level Josephson signals are amplified to volt-level CMOS digital signals by a hybrid interface amplifier, which is the most challenging part of the memory system. The performance of this amplifier is optimized by minimizing its parasitic capacitance loading. The 4-K operation of short-channel CMOS devices and circuits is reviewed, and a complete 4-K CMOS BSIM3 model, which has been verified by experiments, is discussed. The memory bit-line output currents are detected by ultralow-power high-speed Josephson devices. Here, we report the first high-frequency access-time measurements on the full critical path showing 600 ps for a single bit. We discuss future designs made to reduce the crosstalk and improve margins, as well as plans to reduce power dissipation and latency.      

Functional inversion and communication complexity

We study the relationship between the multiparty communication complexity of functions over certain communication topologies and the complexity of inverting those functions. We show that if a function ofn variables has aring-protocol or atree-protocol of communication complexity bounded by ϕ, then there is a circuit of size that computes an inverse of the function. Consequently, we prove that although invertingNC ⁰ Boolean circuits isNP-hard, planarNC ¹ Boolean circuits can be inverted inNC, and hence in polynomial time. From the ring-protocol theorem, we derive an ω(n logn) lower bound on the VLSI area required to lay out any one-way function. Our results on inverting boolean circuits can be extended to algebraic circuits over finite rings. We prove that on certain topologies no one-way function can be computed with low communication complexity. The preliminary version of this paper appeared inCRYPTO 91. This work was supported in part by National Science Foundation Grant DCR-8713489. Part of this work was done while the author was at the School of Computer Science, Carnegie Mellon University, Pittsburgh, PA 15213, U.S.A. Current address: Department of Mathematics, Massachusetts Institute of Technology, Cambridge, MA 02139, U.S.A.     

Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing

Circuit architecture for parallel data processing directly carried out on the hardware have been developed based on a high-functionality transistor, neuron MOSFET (neuMOS or MOS for short). In the MOS data sorting circuit, multiple analog input data are numbered in binary codes according to the order of their magnitudes after a single ramp voltage scan. A MOS motion-vector detector has been developed for on-chip moving image processing based on x- and y-projection data. The circuit can find the movement of an image in two successive frames within a few 100 nsec. The projection-data-based motion detection algorithm has been tested by computer simulation. Test circuits were fabricated by a double-polysilicon CMOS process and basic operation of the circuits has been demonstrated.     

Synthesis of Log-Domain Filters from First-Order Building Blocks

Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 m and 1.2 m BiCMOS processes.     

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead

The concept of using a microcontroller coupled to re-programmable FPGAs is being used at the heart of Run-Time Reconfigurable (RTR) systems. This paper presents the development of an RTR system for DSP and telecommunication applications. It differs from other systems, in that it treats reconfiguration time as a key design parameter by employing design for reconfiguration where partial reconfiguration is identified in the design of the circuit architecture. Reductions of up to 75% in the implementation time of multiplication, division and square root circuits have been achieved using the Xilinx XC6200 FPGA family. A special hardware/software interface called the Virtual Hardware Handler, has also been developed to support the design approach. It vastly simplifies the reconfiguration operation, reducing it to a simple process of passing pointers and data. The approach has been implemented on a windows-based RTR system.