Architecture of a dual-mode cascaded-loop frequency synthesizer

A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. This approach provides fine resolution and wide bandwidth as well as low phase noises. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs in the second mode. It is simulated that, in an application to a P-GSM 900 system tuning from 890 to 915 MHz with a channel spacing of 200 kHz, the worst case phase spurs are of −100 dBc at an offset frequency of 833 kHz and the linear frequency-switching settling time (to 0.01% of frequency increments) is of 128 μs.     

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$mu$m CMOS

A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.     

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm², and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power     

基于0.35μm SiGe BiCMOS的高纯度频率综合器

介绍了一个基于0.35μm SiGe BiCMOS的整数N频率综合器.通过采用不同工艺来实现不同模块,实现了一个具有良好的杂散和相噪性能的高纯度频率综合器.除环路滤波器外所有的部件均采用差分电路结构.为了进一步减小相位噪声,压控振荡器中采用绑定线来形成谐振.该频率综合器可在2.39～2.72 GHz的频率范围内输出功率OdBm.在100kHz频偏处测得的相位噪声为-95dBc/Hz,在1MHz频偏处测得的相位噪声为-116dBc/Hz.参考频率处杂散小于-72dBc.在3V 的工作电压下,包括输出驱动级在内的整个芯片消耗60mA电流.     

A hybrid CDAC-threshold configuring SAR ADC in 28nm FDSOI CMOS

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The proposed architecture implements binary search through a redundant capacitive DAC for the 5 first MSBs and through programmable comparator thresholds for the remaining 4 LSBs. The DAC capacitance at the front-end remains small enough to achieve high sampling rate with increased input bandwidth. Two asynchronously clocked alternate comparators are used additionally to improve conversion speed. The ADC is designed and simulated in 28 nm FD-SOI CMOS. It consumes 4.1 mW from a 1 V supply, while achieving a SNDR of 52.1 dB and a Figure-of-Merit of 11.4 fJ/conversion-step.     

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-/spl mu/m CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 /spl mu/s.     

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.     

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer’s integrated phase noise is less than 1°(1 kHz to 100 MHz)with a 4.375 GHz carrier(after divide-by-2),and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.     

A Low-Voltage Fast Switching Frequency Synthesizer for FH-SS Applications

This brief presents a novel 2.7-V frequency synthesizer for frequency hopping spread spectrum applications. To accomplish fast switching, the frequency synthesizer utilizes a memory access technique to retrieve the precalibrated and digitized tuning voltage values. The phase noise and the frequency accuracy of the frequency synthesizer are analyzed. The channel efficiency, the frequency switching performance, and the output spectral purity are investigated at 2.4 GHz. Measurement shows that the channel switching time is 5 mus. Thus, the proposed synthesizer is promising for frequency hopping wireless communication. The developed architecture is ready to be used for application-specified integrated circuit design     

Ku波段宽带低噪声雷达频率源的研制

介绍一种低相噪、低杂散、宽带的雷达频率合成器方案的设计和实现,该方案采用超低相噪模拟锁相环芯片,并采用双环环内下混频结构,通过对环路滤波器的精心设计,大幅度改善相位噪声和杂散性能。给出设计过程及测试结果。实验证明该方案是成功的,达到的主要技术指标为:输出频率12.8~14.8 GHz,相位噪声-90 dBc/Hz@1 kHz,杂散-55 dBc,步进间隔50 MHz。     

A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-/spl mu/m CMOS

A phase-locked loop (PLL) frequency synthesizer with an on-chip passive discrete-time loop filter is reported in this paper. The closed loop is robust stable, and a fast switching speed is achieved by creating a stabilization zero in the discrete-time domain. The circuit implementations and system-level analysis results of the proposed architecture are presented. Techniques and design considerations are presented to overcome several potential problems of the proposed architecture, such as finite lock-in range, translation of voltage-controlled oscillator noise into in-band phase noise, and spur degradation due to clock feedthrough of the sampling switch. A 2.4 GHz prototype frequency synthesizer for Bluetooth applications was developed in a 0.25-/spl mu/m CMOS process. The measured results agree with theoretical predictions and demonstrate its high performance.     

A fully integrated CMOS frequency synthesizer with charge-averagingcharge pump and dual-path loop filter for PCS- and cellular-CDMAwireless systems

A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-μm CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency     

A low-spurious fast-hopping MB-OFDM UWB synthesizer

A frequency synthesizer for the ultra-wide band(UWB)group # 1 is proposed.The synthesizer uses a phase locked loop(PLL)and single-sideband(SSB)mixers to generate the three center frequencies of the first band group by mixing 4224 MHz with ±264 MHz and 792 MHz,respectively.A novel multi-QSSB mixer is designed to combine the function of frequency selection and frequency conversion for low power and high linearity.The synthesizer is fabricated in Jazz 0.18-μm RF CMOS technology.The measured reference spur is as low as-69 dBc and the maximum spur is the LO leakage of-32 dBc.A low phase noise of-110 dBc/Hz @ 1 MHz offset and an integrated phase noise of 1.86°are achieved.The hopping time between different bands is less than 1.8 ns.The synthesizer consumes 30 mA from a1.8 V supply.     

A CMOS Frequency Synthesizer Block for MB‐OFDM UWB Systems

A CMOS frequency synthesizer block for multi‐band orthogonal frequency division multiplexing ultra‐wideband systems is proposed. The proposed frequency synthesizer adopts a double‐conversion architecture for simplicity and to mitigate spur suppression requirements for out‐of‐band interferers in 2.4 and 5 GHz bands. Moreover, the frequency synthesizer can consist of the fewest nonlinear components, such as divide‐by‐Ns and a mixer with the proposed frequency plan, leading to the generation of less spurs. To evaluate the feasibility of the proposed idea, the frequency synthesizer block is implemented in 0.18‐µm CMOS technology. The measured sideband suppression ratio is about 32 dBc, and the phase noise is ‐105 dBc/Hz at an offset of 1 MHz. The fabricated chip consumes 17.6 mA from a 1.8 V supply, and the die‐area including pads is 0.9 × 1.1 mm².     

基于Delta-Sigma技术的直接数字频率发生器的设计

直接数字频率合成技术(DDFS)具有很好的频率渐变与很高的频率分辨率,然而该技术却伴随着严重的谐波噪声,主要的谐波噪声是相位截断噪声。该文将介绍一种新型的DDFS结构,该结构采用了Delta-Sigma噪声整形技术,有效地减少由相位截断引入的噪声。经测试,信号的信噪比可以大于60dB,同时减小了硬件的复杂性。     

基于AD9959的频率合成器设计及其应用

AD9959是ADI公司推出的一款高性能的四通道DDS芯片,其最高采样速率为500 Msample/S,每个通道具有独立的32 bit频率控制字,14 bit相位控制字和10 bit DAC.利用其同步性能良好、频率分辨高、控制方式灵活的性能特点,根据Galileo/GPS高精度伪卫星系统的要求设计了一款频率合成器.在设计过程中引入ADS软件辅助分析和仿真,该频率合成器能满足系统杂波抑制、相位噪声等各项指标要求.     

A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction

This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer.A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time.An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current.The digital processor can automatically compensate presetting frequency variation with process and temperature,and control the operation of the auxiliary tuning loop.A 1.2 GHz integer-N synthesizer with 1 MHz reference input Was implemented in a 0.18μm process.The measured results demonstrate that the typical settling time of the synthesizer is less than 3μs,and the phase noise is-108 dBc/Hz@1MHz.The reference spur is-52 dBc.     

基于DDS的低相噪频率综合源设计

分析了相位累加器截断、波形ROM有限字长、DAC等对直接数字频率合成器(DDS)相位噪声的影响，得出了DDS芯片本身对输出信号相位噪声影响很小的结论。给出了采用AD9854芯片构成的低相噪频率综合源的硬件组成以及系统实测的相位噪声、杂散技术指标。     

A low-power segmented nonlinear DAC-based direct digital frequency synthesizer

A 2.5-V CMOS direct digital frequency synthesizer (DDFS) with 12 bits of phase resolution and 11 bits of amplitude resolution is presented. Low power consumption is achieved using a nonlinear digital-to-analog converter (DAC). To further reduce power and area, a new technique is proposed to segment the non-linear DAC into a coarse nonlinear DAC and a number of fine nonlinear sub-DACs. The DDFS fabricated in a 0.25-/spl mu/m CMOS process occupies an active area of 1.4 mm/sup 2/. For a clock frequency of 300 MHz, it consumes 240 mW and the spurious-free dynamic range is less than 51 dB for output frequencies up to 3/8 of the clock frequency.     

A 1-V 5.2-GHz CMOS synthesizer for WLAN applications

A 1-V CMOS frequency synthesizer designed for WLAN 802.11a is presented. Novel circuit designs are demonstrated in the system for low-voltage applications including design of voltage-controlled oscillator and design of programmable divider. Implemented in a 0.18-/spl mu/m CMOS process and operated at 1-V supply voltage, the synthesizer measures phase noise of -136 dBc/Hz at a frequency offset of 20 MHz and spur performance of less than -80 dBc at an offset of 11 MHz. The synthesizer dissipates 27.5 mW from a single 1-V supply and occupies a chip area of 1.03 mm/sup 2/.