A 4800 Bit/s Microprocessor Data Modem

The development of a new 4800 bit/s data modem, based on real-time digital signal processing by program controlled microprocessors, is described. The modem is fully compatible with the CCITT Recommendations V.27 bis and V.27 ter. In the microprocessor modem, all the digital signals are processed by one general purpose microprocessor unit only and no hardware multiplier is employed. A series of processing cycle reduction tactics have allowed an off-the-shelf microprocessor to handle all the modem functions in a real-time environment. Particularly noteworthy, among these tactics, is the use of a decision feedback equalization algorithm. Numbers of multiplications, which are required for a conventional linear equalization, are shown to be obviated with the DFE algorithm. It is also shown that the DFE facilitates a certain timing phase control method. The microprocessor modem is extremely flexible because of its software controlled nature, and through programming it will provide a variety of additional functions.     

An Echo-Cancellation-Based 4800 Bit/s Full-Duplex DDD Modem

In this paper we describe an experimental 4800 bit/s fullduplex DDD modem which has been constructed at Bell Laboratories and AT&T Information Systems. The modem achieves full-duplex operation by using echo cancellation techniques. The main features of the modem's architecture and start-up procedure are discussed in the paper. We also study in detail the characteristics of an echo canceller structure which was found to be particularly attractive for this application. Finally, we present experimental performance results obtained over simulated channels in the laboratory and over telephone loopback facilities.     

A High Performance LSI Digital Signal Processor for Communication

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.     

An Experimental Microprocessor-Implemented 4800 Bit/s Limited Distance Voice Band PSK Modem

A low-cost 4800 bit/s modem is described which is applicable to limited distance, direct-copper channels. The modulation technique is eight-phase PSK and both the transmitter and receiver algorithms are aimed at economy of implementation in digital circuitry. The transmitter uses digitally stored waveform elements, and the detection and clock recovery techniques are based on received signal polarity. The implementation of the transmitter and receiver algorithms in a 6800 microprocessor is described. Some experimental results are given.     

Binary Passband Echo Canceller in a 4800 Bit/s Two-Wire Duplex Modem

This paper deals with the echo cancellation applied to highspeed (4800 bit//s or higher) voiceband data modems. Simple echo cancellers are presented for the whole range of data bit rates from 1200 bit//s to 9600 blt/s. Their structure full=y integrates the modulation process and especially exploits the various relationships existing between the modulation rate and the carrier frequency. The generation of the echo replica is performed by duplicating components of the line echo from simple coded binary symbols processed at the modulation rate only. The implementation of these binary passband echo cancellers can be made quite simple by properly selecting the coded binary symbols from the user's data. The application of these principles to a 4800 bit/s two-wire duplex modem is then highlighted. The essential characteristics of the modem echo canceller are outlined and its implementation with bit slice processors is described. Finally, test results on the switched telephone network and on satellite links are presented.     

On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.     

ADSP系列数字信号处理器件的应用

ADSP是AD公司生产的浮点式DSP系列产品，文中对几种ADSP系列产品特点作了综合描述，指出了它们各自系列的特性和数据处理能力。最后给出了ADSP系列产品应用于数字滤波器的实现方法和程序。     

A Single Chip Digital Signal Processor and Its Application to Real-Time Speech Analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 µm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.     

音频信号的数字处理及其应用设计

提出了2.4G无线影音传输系统中的数字音频传输方案,介绍了AES/EBU数字音频接口标准,并详细阐述了系统的关键技术,包括差错掩盖技术和天线切换技术。采用差错掩盖技术,可以消除“噼啪”声;而运用天线切换技术,提高了音频信号接收质量,有效地抑制干扰,提升了系统的性能。     

一种基于数字信号处理器的媒体处理器结构及设计

设计了一种针对图像、音频、视频等多媒体数据的处理新型结构的媒体处理器。该媒体处理器由一个通用数字信号处理器及多媒体协处理器构成,其指令集包含了通用的数字信号处理指令及扩展的多媒体处理指令。多媒体协处理器中包含了多个专用于多媒体处理的功能模块,可以加速多媒体处理的进行。该媒体处理器具有强大的多媒体处理能力,可实现对JPEG压缩图像、MP3音频流或MPEG2的MP@ML级别的压缩视频流的实时解码。     

A Family of Pure Digital Signal Processing Bit Synchronizers

A sample-correlate-choose-largest (SCCL) algorithm is generalized to design a family of efficient baseband digital signal processing (DSP) bit synchronizers. The common feature among maximal likelihood, minimal likelihood, and zero crossing in designing SCCL type DSP bit synchronizers gives us a possible unified point of view in the general design of synchronizers. Optimal signal waveform of “+---” and “-+++” has been derived for this family of bit synchronizers under the signal bandwidth constraint of four times bit rate along with the performance analysis     

面向雷达信号处理应用的可重构处理器设计

为满足现代雷达的高性能应用需求,文中提出并设计了一种可重构专用处理(RASP)架构。其采用非规则化微结构和混合重构策略,有效提升了并行流水计算的性能;通过兵乓处理机制掩盖DDR读写时间,充分发挥了运算资源的效率。RASP作为硬件加速核嵌入华睿2号DSP芯片并于TSMC 40 nm工艺下完成流片。测试结果显示,RASP完成1 K(1 024)点FFT的运算时间为2.57μs,处理效率高达42%,相比于NoC、MorphoSys、C6678、T4240等处理器,性能提升至1. 9~30倍,效率达到1.25~4 倍。     

高速数字信号处理器RT—A100及其应用

RT－A100可级联高速数字信号处理器是南京电子技术研究所开发的具有自主知识产权的数字信号处理器。该信号处理器与著名的INMOS公司的IMSA100在引脚分配上完全兼容,功能上也完全含盖了IMSA100,并有针对性地进行了改进,在性能上完全超过了IMSA100。本文详细地描述了RT－A100的功能、性能及应用。     

第一讲数字信号处理器概论

IC技术讲座是本刊2005年推出全新的技术类栏目。为了让工程师在设计开发中完善和拓展基础理论与系统知识，丰富应用经验，中电网同清华大学等北京知名院校共同创办了这个栏目，特约知名学者、教授以及著名半导体公司的应用工程师撰写，以系列讲座的方式对热点IC技术进行全面而系统的介绍，涵盖最新技术要点。最先开设的讲座将围绕三大课题：DSP、FPGA和嵌入式系统，每个课题都将连载6期。本期课题从数字信号处理器开始。     

基于数字信号处理器的图像处理系统在激光熔池温度场检测中的应用

激光制造中熔池温度场的检测具有重要的实用价值,温度场是激光加工中重要的技术参量,它直接影响加工质量.研究其分布情况,对于控制激光熔池形貌、改进工艺设计、提高激光加工精度和质量,都具有重要意义.提出了基于数字信号处理器(DSP)图像处理方法,对激光熔池温度场进行检测.采用DSP对图像进行实时处理,处理过程脱离PC机,简便、高效.结果表明,采用该图像处理方法可以得到与激光加工工艺参数相关的激光熔池形貌尺寸、激光熔池温度场二维数值分布等信息.进一步发展,可用于激光加工的在线监控和反馈控制.     

群法及其在LSI/VLSI自动布图设计中的应用

本文系统、深入地研究了LSI/VLSI自动布图设计中的群法问题.引入了一系列新的概念:如稳定群、稳定群的级、绝对封闭群等.得出并证明了稳定群的一些重要性质.本文认为,历史上群法中一种非常重要的评价参量,群强度,是不可靠的,并成功地用稳定群代替.用本群法得到的结果与历史上典型群法得到的结果进行比较,结论是非常令人满意的.     

高速数字信号处理器ADSP—2181及其顷数据采集处理卡中的应用

本文就ＡＤＳＰ－２１８１的基本结构与性能做一简要介绍,然后根据我们开发的一种数据采集处理卡,介绍一下ＡＤＳＰ－２１８１在实际中的应用,最后就应用该信号处理器中所应注意的一些问题谈几点体会。     

Nios Ⅱ处理器在数字信号处理中的应用

本文介绍了一种基于嵌入式软核处理器Nios II实现FFT算法的方法;分析了新一代Nios II内核处理器的特点,并从硬件和软件两个方面来论述Nios II系统设计的开发流程;最后,分析了该系统在数字信号处理领域的应用价值.     

高速数字信号处理器ADSP-2181及其在数据采集处理卡中的应用

本文就ADSP-2181的基本结构与性能做一简要介绍,然后根据我们开发的一种数据采集处理卡,介绍一下ADSP-2181在实际中的应用,最后就应用该信号处理器中所应注意的一些问题谈几点体会.     

Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor

This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resources of the 16-bit fixed-point DSP. It is shown that the whole codec computation can be accomplished in about 2350 machine cycles. Thus, two FDSP-3 chips operating at 10 MHz machine cycle can handle the whole computation. The paper also covers the comparison of straight fixed-point format and the G.721 realization, and briefly examines the compatibility issue between these two methods.