A 4800 Bit/s Microprocessor Data Modem

The development of a new 4800 bit/s data modem, based on real-time digital signal processing by program controlled microprocessors, is described. The modem is fully compatible with the CCITT Recommendations V.27 bis and V.27 ter. In the microprocessor modem, all the digital signals are processed by one general purpose microprocessor unit only and no hardware multiplier is employed. A series of processing cycle reduction tactics have allowed an off-the-shelf microprocessor to handle all the modem functions in a real-time environment. Particularly noteworthy, among these tactics, is the use of a decision feedback equalization algorithm. Numbers of multiplications, which are required for a conventional linear equalization, are shown to be obviated with the DFE algorithm. It is also shown that the DFE facilitates a certain timing phase control method. The microprocessor modem is extremely flexible because of its software controlled nature, and through programming it will provide a variety of additional functions.     

An Echo-Cancellation-Based 4800 Bit/s Full-Duplex DDD Modem

In this paper we describe an experimental 4800 bit/s fullduplex DDD modem which has been constructed at Bell Laboratories and AT&T Information Systems. The modem achieves full-duplex operation by using echo cancellation techniques. The main features of the modem's architecture and start-up procedure are discussed in the paper. We also study in detail the characteristics of an echo canceller structure which was found to be particularly attractive for this application. Finally, we present experimental performance results obtained over simulated channels in the laboratory and over telephone loopback facilities.     

A High Performance LSI Digital Signal Processor for Communication

This paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail.     

Binary Passband Echo Canceller in a 4800 Bit/s Two-Wire Duplex Modem

This paper deals with the echo cancellation applied to highspeed (4800 bit//s or higher) voiceband data modems. Simple echo cancellers are presented for the whole range of data bit rates from 1200 bit//s to 9600 blt/s. Their structure full=y integrates the modulation process and especially exploits the various relationships existing between the modulation rate and the carrier frequency. The generation of the echo replica is performed by duplicating components of the line echo from simple coded binary symbols processed at the modulation rate only. The implementation of these binary passband echo cancellers can be made quite simple by properly selecting the coded binary symbols from the user's data. The application of these principles to a 4800 bit/s two-wire duplex modem is then highlighted. The essential characteristics of the modem echo canceller are outlined and its implementation with bit slice processors is described. Finally, test results on the switched telephone network and on satellite links are presented.     

An Experimental Microprocessor-Implemented 4800 Bit/s Limited Distance Voice Band PSK Modem

A low-cost 4800 bit/s modem is described which is applicable to limited distance, direct-copper channels. The modulation technique is eight-phase PSK and both the transmitter and receiver algorithms are aimed at economy of implementation in digital circuitry. The transmitter uses digitally stored waveform elements, and the detection and clock recovery techniques are based on received signal polarity. The implementation of the transmitter and receiver algorithms in a 6800 microprocessor is described. Some experimental results are given.     

On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.     

ADSP系列数字信号处理器件的应用

ADSP是AD公司生产的浮点式DSP系列产品,文中对几种ADSP系列产品特点作了综合描述,指出了它们各自系列的特性和数据处理能力。最后给出了ADSP系列产品应用于数字滤波器的实现方法和程序。     

A Single Chip Digital Signal Processor and Its Application to Real-Time Speech Analysis

A single chip high-performance digital signal processor (HSP) has been developed for speech, telecommunication, and other applications. The HSP uses 3 µm CMOS technology and its architecture features floating point arithmetic and pipeline structure. By adoption of floating point arithmetic, data covering a wide dynamic range (up to 32 bits) can be manipulated. The input clock frequency is 16 MHz, and the instruction cycle time is 250 ns. Efficient signal processing instructions and a large internal memory (program ROM: 512 words; data RAM: 200 words; data ROM: 128 words) make it possible to construct a compact speech analysis circuit by the LPC (PARCOR) method with two HSP's. This paper describes HSP architecture, LSI design, and a speech analysis application.     

音频信号的数字处理及其应用设计

提出了2.4G无线影音传输系统中的数字音频传输方案,介绍了AES/EBU数字音频接口标准,并详细阐述了系统的关键技术,包括差错掩盖技术和天线切换技术。采用差错掩盖技术,可以消除“噼啪”声;而运用天线切换技术,提高了音频信号接收质量,有效地抑制干扰,提升了系统的性能。     

A Family of Pure Digital Signal Processing Bit Synchronizers

A sample-correlate-choose-largest (SCCL) algorithm is generalized to design a family of efficient baseband digital signal processing (DSP) bit synchronizers. The common feature among maximal likelihood, minimal likelihood, and zero crossing in designing SCCL type DSP bit synchronizers gives us a possible unified point of view in the general design of synchronizers. Optimal signal waveform of “+---” and “-+++” has been derived for this family of bit synchronizers under the signal bandwidth constraint of four times bit rate along with the performance analysis     

第一讲数字信号处理器概论

IC技术讲座是本刊2005年推出全新的技术类栏目。为了让工程师在设计开发中完善和拓展基础理论与系统知识，丰富应用经验，中电网同清华大学等北京知名院校共同创办了这个栏目，特约知名学者、教授以及著名半导体公司的应用工程师撰写，以系列讲座的方式对热点IC技术进行全面而系统的介绍，涵盖最新技术要点。最先开设的讲座将围绕三大课题：DSP、FPGA和嵌入式系统，每个课题都将连载6期。本期课题从数字信号处理器开始。     

基于数字信号处理器的图像处理系统在激光熔池温度场检测中的应用

激光制造中熔池温度场的检测具有重要的实用价值,温度场是激光加工中重要的技术参量,它直接影响加工质量.研究其分布情况,对于控制激光熔池形貌、改进工艺设计、提高激光加工精度和质量,都具有重要意义.提出了基于数字信号处理器(DSP)图像处理方法,对激光熔池温度场进行检测.采用DSP对图像进行实时处理,处理过程脱离PC机,简便、高效.结果表明,采用该图像处理方法可以得到与激光加工工艺参数相关的激光熔池形貌尺寸、激光熔池温度场二维数值分布等信息.进一步发展,可用于激光加工的在线监控和反馈控制.     

Implementation of a 32 Kbit/s ADPCM Codec Using a General-Purpose Digital Signal Processor

This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resources of the 16-bit fixed-point DSP. It is shown that the whole codec computation can be accomplished in about 2350 machine cycles. Thus, two FDSP-3 chips operating at 10 MHz machine cycle can handle the whole computation. The paper also covers the comparison of straight fixed-point format and the G.721 realization, and briefly examines the compatibility issue between these two methods.     

DSP最小应用系统的设计

介绍了基于DSP(数字信号处理)的最小应用系统的整体设计过程。系统采用TMS320VC5402作为主控芯片;ADC0809完成数据的采样及A/D转换,通过TMS320VC5402处理后,由DAC0832完成D/A转换并输出;外部存储器采用通用EPROM,TMS320VC5402采用8位并行EPROM引导方式;并加入了标准的14针JTAG接口,便于系统的调试与仿真。     

数字信号处理及其通信系统设计

本文通过对数字信号处理器、外围支持系统、信号输入输出及其数字通信系统的综合分析讨论，总结了高速数字信号处理及其通信系统的一般设计原则和技巧，并以此设计了一个多速率的实时语音编解码及其通信系统，得到了良好的实际应用效果。     

256 QAM Modem for Multicarrier 400 Mbit/s Digital Radio

This paper describes the performance of a 256 QAM modem with 400 Mbit / s transmission capacity. A variety of novel techniques are introduced as ways to achieve good performance. Key techniques include 1) an accurate 256 QAM modulator employing a new monolithic multiplier IC, 2) a carrier recovery circuit which satisfies such requirements: good phase jitter performance and no false lock phenomenon, 3) a highly stable high-level decision circuit, and 4) a forward error correcting code. As an overall modem performance, BER characteristics and signatures are presented. The equivalent CNR degradations of 1 dB(at BER of 10^-4) and 2 dB (at BER of 10^-9)are obtained using a single Lee-error correcting code and a seven-tap baseband transversal equalizer. The residual bit errors are decreased below the order of 10^-10. The performance of a 256 QAM multicarrier modem has given prospect for the development of 400 Mbit/s digital microwave radio system.     

无线数字基带处理器CMX980特性及其在调制解调中的应用

CMX980是一种通用的同相和正交（I/Q）兼容的无线数字基带处理器,其基带处理能力（ADC、DAC、数字FIR,π/4DQPSK调制器等）可满足TETRA（Trans-European Trunked Radio）和其他无线数字移动通信系统的要求,本文介绍了CMX980的特性及其在TETRA调制解调基带处理中的应用。     

同步突发静态RAM(SBSRAM)及其在DSP系统中的应用

介绍同步突发静态RAM的特点及结构，并就其与DSP(digital signal processor)的接口信号、控制寄存器、读写操作、时序设计，数据访问时的等待状态等进行讨论。最后给出一个SBSRAM在信号处理系统中的应用实例。     

ADSP-TS101S TigerSHARC处理器在信号处理中的应用

本文介绍了利用AD公司新一代高性能DSP芯片TigerSHARC TS101S构成的一个信号处理系统.文中讲述了此DSP芯片的特点,DSP芯片在信号处理系统中的应用以及电路设计.本文对于其它工程设计具有参考价值.