A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

具有L型低阻导电通道的介质场增强SOI LDMOS

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

Properties of silicon-on-insulator structures and devices

The physical grounds for making SOI structures by the DeleCut (ion irradiated deleted oxide cut) method are considered. This method is a modification of the commonly known Smart Cut? technique and aims at eliminating the disadvantages of the basic method [1]. The proposed method makes it possible to considerably lower the annealing temperature and the content of radiation defects in SOI structures. It allows the thickness of a split-off Si layer and a transition layer between the SOI layer and a buried oxide to be reduced. The method also reduces the nonuniformity in the thickness of the SOI layer and the insulator to several nanometers. By using DeleCut, new SOI structures were formed on wafers with diameters as large as 150 mm; the structures included dislocation-free SOI layers of 0.003–1.7 μm in thickness and a buried thermal SiO₂ oxide (0.05–0.5 μm). These structures have good electrical characteristics, which is supported by fabricating the submicrometer (0.2–0.5 μm) SOI-based CMOS transistors and test integrated circuits. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 35, No. 9, 2001, pp. 1075–1083. Original Russian Text Copyright ? 2001 by Popov, Antonova, Frantsuzov, Safronov, Feofanov, Naumova, Kilanov.     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

A NEW STRUCTURE AND ITS ANALYTICAL BREAKDOWN MODEL OF HIGH VOLTAGE SOI DEVICE WITH STEP UNMOVABLE SURFACE CHARGES OF BURIED OXIDE LAYER

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.     

Complementary charge islands structure for a high voltage device of partial-SOI

A new partial-SOI(PSOI) high voltage device structure named CNCI PSOI(complementary n~+-charge islands PSOI) is proposed.CNCI PSOI is characterized by equidistant high concentration n~+ -regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device.When a high voltage is applied to the device,complementary holes and electron islands are formed on the two n~+-regions on the top and bottom interfaces,therefore effectively enhancing the electric field of the dielectric buried layer(E_I) and increasing the breakdown voltage (BV),alleviating the self-heating effect(SHE) by the silicon window under the source.An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results.BV and E_I,of the CNCI PSOI LDMOS increase to 591 V and 512 V/μm from 216 V and 81.4 V/μm of the conventional PSOI with a lower SHE,respectively.The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.     

A thick SOI UVLD LIGBT on partial membrane

A thick SOI LIGBT structure with a combination of uniform and variation in lateral doping profiles （UVLD） on partial membrane（UVLD PM LIGBT） is proposed.The silicon substrate under the drift region is selectively etched to remove the charge beneath the buried oxide so that the potential lines can release below the membrane,resulting in an enhanced breakdown voltage.Moreover,the thick SOI LIGBT with the advantage of a large current flowing and a thermal diffusing area achieves a strong current carrying capability and a low junction temperature.The current carrying capability(K_Anode = 6 V,V_Gate = 15 V) increases by 16%and the maximal junction temperature（1 mW/μm） decreases by 30 K in comparison with that of a conventional thin SOI structure.     

Few-mode vertical-cavity surface-emitting lasers for space-division multiplexing

In order to choose the proper radius of oxide aperture for few-mode vertical-cavity surface-emitting lasers (VCSELs), the influences of oxide aperture size on the multi-transverse-mode behaviors are investigated in detail. By establishing the effective refractive index model to simulate VCSELs with different radii of oxide apertures, the wavelength and corresponding order of different modes are obtained. VCSELs with three kinds of oxide apertures are manufactured. Then the multi-transverse-mode spectra and near-field are measured. It is found that when the radius is between 1.5 and 4.5 μm, few-mode VCSELs can be implemented. The 2.5 μm VCSEL manufactured in this paper only emits LP01 mode and LP21 mode. Since the space distance between the two modes is 2 μm, it is expected to realize direct-modulation few-mode VCSELs by channel etching or ion implantation between the two modes.     

Technology innovation and process integrations for sub-100nm gate patterning

This paper presents a brief overview of the Applied Centura(R)DPS(R)system,configured with silicon etch DPS Ⅱ chamber, with emphasis on discussing tuning capability for CD uniformity control. It also presents the studies of etch process chemistry and film integration impact for an overall successful gate patterning development. Discussions will focus on resolutions to key issues, such as CD uniformity, line-edge roughness, and multilayer film etching integration.     

Complete approach to automatic identification and sub-pixel center location for ellipse feature

To meet the need of automatic image features extraction with high precision in visual inspection, a complete approach to automatic identification and sub-pixel center location for similar-ellipse feature is proposed. In the method, the feature area is identified automatically based on the edge attribute, and the sub-pixel center location is accomplished with the leastsquare algorithm. It shows that the method is valid, practical, and has high precision by experiment. Meanwhile this method can meet the need of instrumentation of visual inspection because of easy realization and without man-machine interaction.     

White organic light-emitting devices based on fac tris（2- phenylpyridine） iridium sensitized 5,6,11,12-tetraphenylnap -hthacene

We have fabricated the white organic light-emitting devices （WOLEDs） based on 4,4＇ -bis（2,2 -diphenyl vinyl）-1,1＇ - biphenyl （DPVBi） and phosphorescence sensitized 5,6,11,12,-tetraphenylnaphthacene （rubrene）. The device structure is ITO/2T-NATA （20 nm）/NPBX （20 nm）/CBP： x%Ir（ppy）3：0.5% rubrene （8 nm）/NPBX （5 nm）/DPVBi （30 nm）/Alq（30 nm）/LiF（0.5 nm）/A1. In the devices, DPVBi acts as a blue light-emitting layer, the rubrene is sensitized by a phosphorescent material, fac tris （2-phenylpyridine） iridium [Ir（ppy）3], acts as a yellow light-emitting layer, and N,N＇ -bis- （1-naphthyl）- N,N＇ -diphenyl -1, 1＇ -biphenyl-4,4＇ -diamine （NPBX） acts as a hole transporting and exciton blocker layer, respectively. When the concentration of Ir （PPY）3 is 6wt%, the maximum luminance is 24960 cd/m^2 at an applied voltage of 15 V, and the maximum luminous efficiency is 5.17 cd/A at an applied voltage of 8 V.     

小角度扩展相关性近似算法分析

本论文提出一种在多天线MIMO信道相关性建模中小角度扩展近似理论算法,并应用于分析MIMO系统性能。分析中分别对三种不同角能量分布情况下的空间相关性研发快速近似计算法,并同时提出双模(Bi-Modal)角能量分布情况下的近似运算。通过分析这些新方法的近似效率,可以得到计算简单、复杂度低、而且符合实际的MIMO相关信道矩阵,对系统级的快速高效计算法的研究和系统级的评估以及误差分析具有重要的意义。     

Cost-effective test solutions for smart card and other integrated flash applications

From its emergence in the late 1980s as a lower cost alternative to early EEPROM technologies, flash memory has evolved to higher densities and speedsand rapidly growing acceptance in mobile applications.In the process, flash memory devices have placed increased test requirements on manufacturers. Today, as flash device test grows in importance in China, manufacturers face growing pressure for reduced cost-oftest, increased throughput and greater return on investment for test equipment. At the same time, the move to integrated flash packages for contactless smart card applications adds a significant further challenge to manufacturers seeking rapid, low-cost test.     

Theoretical analysis of the relationship between the Brillouin gain coefficient and the strain in the optical-fiber sensors

The relation between the power of the Brillouin signal and the strain is one of the bases of the distributed fiber sensors of temperature and strain. The coefficient of the Bfillouin gain can be changed by the temperature and the strain that will affect the power of the Brillouin scattering. The relation between the change of the Brillouin gain coefficient and the strain is thought to be linear by many researchers. However, it is not always linear based on the theoretical analysis and numerical simulation. Therefore, errors will be caused if the relation between the change of the Brillouin gain coefficient and the strain is regarded as to be linear approximately for measuring the temperature and the strain. For this reason, the influence of the parameters on the Brillouin gain coefficient is proposed through theoretical analysis and numerical simulation.     

Novel fiber-optical interferometer with miniaturized probe for in-hole measurements

Today, micro-system technology and the development of new MEMS （Micro-Electro-Mechanical Systems） are emerging rapidly. In order for this development to become a success in the long run, measurement systems have to ensure product quality. Most often, MEMS have to be tested by means of functionality or destructive tests. One reason for this is that there are no suitable systems or sensing probes available which can be used for the measurement of quasi inaccessible features like small holes or cavities. We present a measurement system that could be used for these kinds of measurements. The system combines a fiber optical, miniaturized sensing probe with low-coherence interferometry, so that absolute distance measurements with nanometer accuracy are possible.     

An Improved parallel thinning algorithm with two subiterations

The parallel thinning algorithm with two subiterations is improved in this paper. By analyzing the notions of connected components and passes, a conclusion is drawn that the number of passes and the number of eight-connected components are equal. Then the expression of the number of eight-connected components is obtained which replaces the old one in the algorithm. And a reserving condition is proposed by experiments, which alleviates the excess deletion where a diagonal line and a beeline intersect. The experimental results demonstrate that the thinned curve is almost located in the middle of the original curve connectivelv with single pixel width and the processing speed is high.     

A Versatile Mixed-Signal Pin Approach for Cost-Effective Test of Automotive ICs

Integrated circuits (ICs) intended for increasingly sophisticated automotive applications bring unique test demands. Advanced ICs for applications such as highly integrated automatic braking system (ABS) and airbag controllers combine high voltage digital channels, significant VI demands and precise timing capability. Along with continued missioncritical reliability concerns, the trend toward higher voltage operation and increased device integration requires specialized test capabilities able to extend across the wide operating ranges found in automotive applications. Among these capabilities, automotive test requirements increasingly dictate a need for a cost-effective versatile mixed-signal pin electronics with very high data rates reaching up to 50MHz with a voltage swing of-2 V to +28 V.     

Optical vibration and deviation measurement of rotating machine parts

It is of interest to get appropriate information about the dynamic behaviour of rotating machinery parts in service. This paper presents an approach of optical vibration and deviation measurement of such parts. Essential of this method is an image derotator combined with a high speed camera or a laser doppler vibrometer （LDV）.