基于CMMB系统的LDPC译码器的设计与实现

根据CMMB中LDPC码校验矩阵的结构特点,提出了一种部分并行译码结构的实现方法,并在XILINX的VirtexIV的XC4VLX80型FPGA上实现了这种结构。该设计充分利用了LDPC校验矩阵的规律,采用了一种适当的硬件结构和独特的存储器调用控制策略,故可在保证高性能和较大吞吐率的情况下,以较少的硬件资源实现两种码率的复用。     

面向IEEE802.16e的高效LDPC编码器设计

基于矩阵乘法的高斯消元法提出了一种通用的LDPC编码器结构,该结构使用移位寄存器和简单的选线实现了复杂的矩阵向量相乘运算并且不需要存储庞大的校验矩阵。然后根据IEEE 802.16e标准中对校验矩阵的定义,利用FPGA实现了编码器的硬件结构,并且由仿真结果可知这种LDPC编码器结构降低了逻辑资源开销,提高了编码速度。     

一种π-旋转LDPC码的Min-Sum译码算法

π-旋转LDPC码结构规则,存储量少,易于硬件实现。给出一种新的π-旋转LDPC码编码、解码方法。根据校验矩阵的半规则化结构,给出校验矩阵行索引和列索引矩阵的构造方法。基于这种索引矩阵,给出一种运算量较少的编码、Min-Sum译码算法。这种编译码方法甚至不需要构造真正的H矩阵。     

π-旋转LDPC码的高效并行编译码结构设计

该文设计了一种π-旋转LDPC码并行编/译码电路结构.利用π-旋转LDPC码的规则化旋转结构,编码、译码电路实现了分组并行处理.在信息迭代过程中,利用校验矩阵的旋转结构,使用一种二维数组存储译码迭代信息,不需要地址索引、只需通过映射即可取出所需参与运算的变量/校验信息,实现了迭代信息的分散存储、映射提取.这种分组、旋转...     

一种可快速编码的QC-LDPC码构造新方法

为解决LDPC码的编码复杂度问题,使其更易于硬件实现,提出了一种可快速编码的准循环LDPC码构造方法。该方法以基于循环置换矩阵的准循环LDPC码为基础,通过适当的打孔和行置换操作,使构造码的校验矩阵具有准双对角线结构,可利用校验矩阵直接进行快速编码,有效降低了LDPC码的编码复杂度。仿真结果表明,与IEEE 802.16e中的LDPC码相比,新方法构造的LDPC码在低编码复杂度的基础上获得了更好的纠错性能。     

一种基于均匀环路的LDPC码校验矩阵的构造方法

LDPC码作为一种新的接近香农极限的信道编码方式,引起了广泛的注意。本文在总结出LDPC码校验矩阵的初等变换环路不变性和环路长度性质的基础上,提出了一种基于均匀环路的校验矩阵构造的新思路,而且还可以通过校验矩阵的矩阵初等变换得到其校验矩阵簇,在该簇中可以挑选编码复杂度低的LDPC码用在实际传输中。     

一种基于本原多项式的LDPC码构建新算法

在分析传统LDPC编码方式的基础上,提出一种基于本原多项式实现LDPC编码的新方法.根据特定LDPC码长选择合适的本原多项式作为子矩阵,对子矩阵进行行列分解、组合,最终构建LDPC码校验矩阵H.仿真实验结果和工程应用证明:新算法构建的LDPC码在恶劣的通信环境下,误码率、误帧率优于传统Mackay - LDPC码,具有...     

准规则Q矩阵LDPC码编码器设计

设计了一种准规则Q矩阵LDPC码编码器.该编码器基于准规则Q矩阵LDPC码的校验矩阵,其编码复杂度与信息位的长度成正比,有效降低了编码复杂度和设计难度.在Quartus Ⅱ平台上用FPGA实现了该编码器,结果证明其硬件资源占用很少.     

基于FPGA的LDPC编码设计

针对低密度奇偶校验码(简称LDPC码)的直接编码运算量较大、复杂度高,根据Richardson和Urbanke(RU)建议的编码方案,介绍一种适于在FPGA上实现,利用有效校验矩阵来降低编码复杂度的LDPC编码方案,给出了编码器设计实现的原理和编码器的结构和基本组成.在Quartus Ⅱ 7.2软件平台上采用基于FPGA的VHDL语言实现了有效的编码过程.结果表明:此方案在保证高效可靠传输的同时降低了实现的复杂度.这种编码方案可灵活应用于不同的校验矩阵H,码长和码率的系统中.     

一种改进的基于有限域的准循环LDPC码设计方法

结合有限域方法和具有简单递归编码特性的Tam结构,提出了一种新的准循环LDPC码构造方法.该方法首先利用有限域方法构造出校验矩阵,并得到其相应的指数矩阵,接着采用具有Tam结构的校验矩阵对应的二元基矩阵,两者进行掩膜运算(mask),得到新的指数矩阵,最后构造出的准循环LDPC码兼具有限域方法的良好纠错特性和Tam结构的简单递归编码特性.仿真结果表明,所提方法构造的准循环LDPC码的BER(Bit Error Rate)性能要优于Tam码和802.16e码.     

On the Construction of Quasi-Systematic Block-Circulant LDPC Codes

A class of quasi-systematic block-circulant LDPC (QSBC-LDPC) Codes is proposed. The parity-check matrix of a QSBC-LDPC code is a sparse block-circulant matrix with a quasi-systematic structure. Due to the special structure of the parity-check matrix, only limited memories, XOR computations and cyclic-shifting operations are needed in the recursive encoding process of the QSBC-LDPC codes. Simulations show that the QSBC-LDPC codes provide remarkable performance improvement with low encoding complexity.     

GB20600标准的LDPC码的改进

尽管LDPC码已经被GB20600标准采纳作为信道编码,与其它LDPC码相比,在同样码长和码率的情况下,GB20600 LDPC码误码率性能并非最佳;GB20600标准的LDPC码的码长达7493,存在编码复杂性问题,但是GB20600 LDPC码未采用基于校验矩阵的快速算法,这给GB20600 LDPC编解码器的硬件实现带来较大的困难。本文在现有GB20600 LDPC码的设计框架下,对GB20600中LDPC码的校验矩阵进行了修改,在此基础上提出一种有效的LDPC码的快速迭代算法,使编解码器的硬件易于实现。改进后的LDPC码的编码算法具有较低的实现复杂度。仿真结果表明,改进后的LDPC码的误包率性能优于现GB20600中LDPC码的误包率性能。      

Novel Construction and Optimization of LDPC Codes for NC-OFDM Cognitive Radio Systems

In this paper, a random Low-Density Parity-Check (LDPC) code is proposed for Noncontiguous Orthogonal Frequency Division Multiplexing (NC-OFDM) Cognitive Radio (CR) systems. Unlike other encoding schemes which achieve a system code rate of only 1/4 when half of the subcarriers are active, the proposed scheme achieves a system code rate of 1/2. The LDPC code is used to enhance the data transmission rate. A new channel model comprised of a binary erasure channel concatenated with an uncorrelated fading channel and an AWGN channel is adopted for NC-OFDM CR systems. Moreover, the adopted channel model is employed with density evolution algorithm to obtain good degree distribution pairs for the LDPC code. Thereafter, a modified shortest-path algorithm is used to construct the parity-check matrix for the LDPC code. Simulation results show that the proposed LDPC code performs well in terms of both error rate and data transmission rate.     

Construction of quasi‐cyclic low‐density parity‐check codes with low encoding complexity

Low encoding complexity is very important for quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes used in wireless communication systems. In this paper, a new scheme is presented to construct QC‐LDPC codes with low encoding complexity. This scheme is called two‐stage particle swarm optimization (TS‐PSO) algorithm, in which both the threshold and girth distribution of QC‐LDPC codes are considered. The proposed scheme is composed of two stages. In the first stage, we construct a binary base matrix of QC‐LDPC code with the best threshold. The matrix is constructed by combining a binary PSO algorithm and the protograph extrinsic information transfer (PEXIT) method. In the second stage, we search an exponent matrix of the QC‐LDPC code with the best girth distribution. This exponent matrix is based on the base matrix obtained in the first stage. Consequently, the parity‐check matrix of the QC‐LDPC code with the best threshold and best girth distribution are constructed. Furthermore, bit error rate performances are compared for the QC‐LDPC codes constructed by proposed scheme, the QC‐LDPC code in 802.16e standard, and the QC‐LDPC code in Tam's study. Simulation results show that the QC‐LDPC codes proposed in this study are superior to both the 802.16e code and the Tam code on the additive white Gaussian noise (AWGN) and Rayleigh channels. Moreover, proposed scheme is easily implemented, and is flexible and effective for constructing QC‐LDPC codes with low encoding complexity. Copyright © 2012 John Wiley & Sons, Ltd.     

光通信系统中基于LDPC码的SFEC码型研究

基于光通信系统中低密度奇偶校验(LDPC)码型的构造原则和构造方法,构造了适用于光通信系统中冗余度为6.69%的新颖LDPC(3969,3720)和冗余度为4.56%的新颖LDPC(8281,7920)码。仿真分析表明:在10-12的误码率(BER)时,这两种新颖码型在迭代18次后的净编码增益(NCG)分别比ITU-TG.975中RS(255,236)码的NCG大1.63dB和1.49dB,并且LDPC码的译码可在硬件上并行实现;这两种新颖码型的译码速度相当快,与ITU-TG.975.1中级联码型相比,这两种LDPC码的实现复杂度要低得多,可在将来的硬件实现中节省存储空间和减少计算量。因而,所构造的这两种新颖LDPC码型都可作为超验前向纠错(SFEC)码的候选码型。     

On CS Image Reconstruction Using LDPC Code Over Radio Mobile Channel

In this work, the effect of additive white Gaussian noise and fading channel on the compressed sensing or compressive sampling (CS) image reconstruction process are demonstrated. First, the work suggests encoding of the sensed samples by low density parity check code (LDPC) before transmission. It is well known that longer is the length of the LDPC codes better (lower) is the bit error rate (BER) performance. Thus to improve CS reconstruction a method to construct a larger length but 4 cycle free irregular LDPC code structure is also proposed. The code construction is based on the LDPC code in IEEE WiMAX standard. The proposed CS-LDPC structure is then extended for \(4^n\)-QAM to find an optimal set of thresholds by minimizing BER (equivalently symbol error rate) using differential evolution (DE). The algorithm works on the log likelihood ratio values obtained by LDPC decoding. Extensive simulation results show the efficacy of the use of LDPC codes and the trade-off in code rate and measurements on reconstruction quality. Improved performance with the proposed DE based demodulation is also demonstrated.     

Decoding and Design of LDPC Codes for High-Order Modulations

A concatenated code model is proposed for high-order low-density parity-check (LDPC) coded modulations. A corresponding concatenated-code belief propagation (CCBP) decoding algorithm is derived for our proposed concatenated code. Moreover, the design of LDPC codes under the CCBP decoding is developed using extrinsic information transfer (EXIT) charts. Compared with other algorithms, the CCBP method provides an excellent parallel decoding process, and the EXIT-based design method offers highly accurate LDPC code ensembles. Simulation results show that the performance of the proposed CCBP algorithm is superior to that of the conventional belief propagation decoding within a wide range of modulation orders, and the EXIT-based method can design capacity-approaching LDPC codes for high-order modulations.     

误码条件下LDPC码参数的盲估计

针对非合作信号处理中LDPC码（Low-Density Parity-Check）的盲识别问题,提出了一种容错能力较强的开集识别算法.该算法通过对码字矩阵进行高斯约旦消元找到汉明重量较小的"相关列",并根据"相关列"中所包含的约束关系求得LDPC码的校验向量,然后剔除"相关列"中为"1"位置对应的错误码字.若根据高斯约旦消元求校验向量和剔除错误码字进行迭代无法得到更多校验向量,则对得到的这些校验向量进行稀疏化,再进行译码纠错.最后,综合利用校验向量的求解,错误码字的剔除,校验向量稀疏化,LDPC码译码进行迭代,实现LDPC码校验矩阵的有效重建.仿真结果表明,对于IEEE 802.16e标准中的（576,288）LDPC码,在误比特率为0.0022时,本文算法仍可以达到较好的识别效果.     

符合CCSDS标准的动态可重构LDPC编码器的FPGA设计

CCSDS标准的LDPC生成矩阵具有分块循环特征,并且各种码率的生成矩阵的校验部分都可以分解为8×x的形式,提出利用CCSDS标准的LDPC的特点设计动态可重构LDPC编码器。首先提出了LDPC编码器码速率重构的4种模型,然后分析了功能重构的关键技术模块,最后对码速率重构进行了仿真,并对仿真结果和综合结果进行了分析,结果与理论分析一致。     

QC LDPC码低复杂度消环算法

QC LDPC (Quasi-才yclic Low-density Parity-check)是一类半结构化的低密度奇偶校验码,其分块的矩阵结构具有超大规模集成电路实现上的便利,同时保持了优异的纠错性能. 本文针对QC LDPC码的基矩阵,提出一种移位因子的搜索方法及其改进版本。通过对基矩阵的扩展矩阵的Tanner图进行树形展开来进行环的检验,避免了传统算法中的复杂算术操作,降低了复杂度。在采用和IEEE 802.16e中码率为0.5的LDPC码方案相同的基矩阵条件下,本文的算法构造出的QC LDPC码具有更优的环长分布,同时纠错性能也有提升。