一种低成本的硅垂直互连技术

1引言 近年来，随着三维叠层封装技术和MEMS封装技术的发展，硅垂直互连技术正在受到越来越多的重视【1】。这一技术通过在硅片上制作出垂直电互连来实现芯片正面与背面或上下芯片之间的互连，从而缩短了互连线的长度并为芯片提供更为优异的电性能。其应用包括：台面MOS功率器件的倒装芯片封装【2】、垂直集成传感器阵列的制造【3】、RF-MEMS器件的封装【4】、高性能硅基板的开发【5】和芯片的三维叠层封装【6】。     

SiP技术在晶圆级生产中的应用

系统芯片（SoC）旨在采用单一的半导体工艺技术实现完整的系统.系统封装（SiP）则是将各种不同的工艺技术整合到一个小型的芯片封装中.尽管SoC和SiP通常被认为是相互竞争的技术,但两者的共同之处在于：在集成密度、价位和大规模制造方面要和晶圆生产达到平衡点.     

微波多芯片模块技术

论述了微波多芯片模块（MMCM）技术的发展历史、应用领域及工艺进展。着重从芯片互连、基板材料及封装设计等方面讨论了该技术的发展前景,并对我国微电子和MMCM封装技术提出几点建议。     

内嵌协议堆栈的超低功耗单片无线收发芯片nRF24AP1

nRF24AP1是在Nordic公司过去两年里推出的多款高集成度单片CMOS 2．4GHz无线芯片的基础上，采用Nordic最新的技术和超低功耗技术，在一个5X5mm封装中集成有无线传输以及无线互连软件协议堆栈等完整功能的无线收发芯片，该芯片体现了使用、性能和成本的完美结合。由于其具有超低功耗特性并集成了软件堆栈，因而很适合于采用纽扣电池供电的应用场合，同时可用于工业控制、科研、医学等领域，而且比zigBee和蓝牙在成本和低功耗方面更有优势。     

埋置型叠层微系统封装技术

包含微机电系统(MEMS)混合元器件的埋置型叠层封装,此封装工艺为目前用于微电子封装的挠曲基板上芯片(COF)工艺的衍生物.COF是一种高性能、多芯片封装工艺技术,在此封装中把芯片包入模塑塑料基板中,通过在元器件上形成的薄膜结构构成互连.研究的激光融除工艺能够使所选择的COF叠层区域有效融除,而对封装的MEMS器件影响...     

后摩尔时代的封装技术

介绍了在高性能的互连和高速互连芯片(如微处理器)封装方面发挥其巨大优势的TSV互连和3D堆叠的三维封装技术。采用系统级封装(SiP)嵌入无源和有源元件的技术,有助于动态实现高度的3D-SiP尺寸缩减。将多层芯片嵌入在内核基板的腔体中;采用硅的后端工艺将无源元件集成到硅衬底上,与有源元件芯片、MEMS芯片一起形成一个混合集成的器件平台。在追求具有更高性能的未来器件的过程中,业界最为关注的是采用硅通孔(TSV)技术的3D封装、堆叠式封装以及类似在3D上具有优势的技术,并且正悄悄在技术和市场上取得实实在在的进步。随着这些创新技术在更高系统集成中的应用,为系统提供更多的附加功能和特性,推动封装技术进入后摩尔时代。     

集成电路圆片级芯片尺寸封装技术（WLCSP）

1技术创新性 集成电路圆片级芯片封装技术（WLCSP）及其产品属于集成创新,是江阴长电先进封装有限公司结合了铜柱凸块工艺技术及公司自身在封装领域的技术沉淀,开发出的区别于国外技术的新型圆片级芯片封装技术。     

微电子封装技术的新趋势

本文从应用的观点出发简要介绍了各种封装技术在新世纪中的发展趋势。论述了如CSP、BGA 及倒装芯片等先进封装技术在微电子工业中所发挥的重要作用。     

半导体及电子封装技术是发展信息化循环型社会的重要技术基础

信息化程度的高低是衡量一个国家综合国力的重要标志。随着以微电子学为基础的计算机和通讯技术发展迅猛，信息产业已成长为当今世界的第一产业，推动了人类文明的进步。微电子技术是发展电子信息产业和各项高技术中不可缺少的基础，是高技术的关键，微电子领域的两大关键性技术是芯片制造和微电子封装，IC芯片功能的实现，要靠电子封装材料、器件、连接、设计、可靠性评估等诸多方面的支持，它保障着电子设备中几乎所有基础半导体元器件的正常工作，起到了电源供给、信号互连。机械支撑、散热和环境保护的功能。芯片是大脑，电子封装是躯干。据统计，电子封装的产业规模超过1万亿美元，大概是集成电路产业的10倍左右。现代微电子封装技术，不仅影响着信息产业及整个国民经济的发展，也与每个家庭的现代化息息相关。微电子封装是信息产业的核心技术，IC的发展要求更高的微电子材料。     

柱栅阵列的无铅卡组装和返修

IBM已将铜柱栅阵列(CuCGA)互连用作为陶瓷柱栅阵列(CCGA)上锡铅焊料柱的无铅替代品(见图1)。像CCGA一样，CuCGA提供一种高可靠性封装解决方案，可以使用具有优良的电性能和热性能的陶瓷芯片载体。取消铅在微电子封装中的应用的行动增加了大尺寸、高I／O封装的制造复杂性。与新型封装互连结构的开发一致的可制造卡组装和返工工艺的开发对于技术的可接收性是至关重要的。设计的铜柱栅阵列(CuCGA)互连可满足可制造性、可靠性和电性能等多方面的要求。可制造性的结构优化重点是在制造处理过程中保证柱的牢固性和具有便捷的卡组装工艺。最终卡上的焊点对于互连的可靠性是至关重要的。互连的几何形状还影响到电性能【1】。评估这些有竞争性因素决定着最后的柱设计【2】。本文重点讨论了CuCGA卡组装和返工工艺的开发和可靠性评估。工艺开发的目的是将成功的SMT组装工艺用于CCGA，以便开发出标准的无铅SMT工艺。将CuCGA组装工艺成功地集成于锡银一铜(SnAgCu，或者SAC)卡组装工艺的开发中，这对于贴装、再流和返修领域都将是一个挑战。本文将讨论通过可靠性评估说明这些工艺的优化和成功结果的实例。     

MEMS中的封装技术研究

MEMS中的封装工艺与半导体工艺中的封装具有一定的相似性 ,因此 ,早期MEMS的封装大多借用半导体中现成的工艺。本文首先介绍了封装的主要形式 ,然后着重阐述了晶圆级封装与芯片级封装[1] 。最后给出了一些商业化的实例     

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.     

微电子封装无铅钎焊的可靠性研究

本文阐述了微电子封装聚用无铅钎料的必要性。概述了无钎铅料的研究现状，最后着重分析讨论了微电子封装无铅钎焊的可靠性问题。     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Improved stability of contact resistance of low melting point alloy incorporated isotropically conductive adhesives

With the driving force of "green" revolution in the electronics industry, tremendous efforts have been made in pursuing lead-free alternatives. Although lately lead-free alloys have drawn a lot of attention, their technical weaknesses, such as high processing temperature, poor wetting and high surface tension, limit their applications on the thermally sensitive, flexible, nonsolderable substrates and the ultra-fine pitch size flip chip interconnection. Conventional isotropically conductive adhesives (ICAs) have been used widely in surface mount and die-attach technologies for electrical interconnection and heat dissipation. The low temperature processing of ICAs is one of the major advantages over lead-free solders, which brings a low system stress, simple manufacture process and the like. In order to enhance the contact resistance of ICAs, the low melting point alloy (LMA) incorporating technology has been developed by our group. In this paper, LMA fusing methods were studied, since nonfused LMA in ICAs after a curing process can adversely affect the physical property and contact resistance stability. A differential scanning calorimeter (DSC) was used for the basic examination of depleting rate of LMAs in the typical ICAs. The cross-sectional morphology, LMA distribution and intermetallic compound were investigated by a scanning electron microscope (SEM). In addition, contact resistance for the ICA formulation incorporated with LMAs under elevated temperature and humidity was evaluated.     

电子组装中的复杂技术

随着电子产品向小、轻、薄、多功能方向的快速发展,新型元器件不断出现.新型元器件由于其封装特殊,价格昂贵而且易损坏,因此组装工艺技术复杂.由此引发了组装设备、工艺、工装、材料、检测、返修等一系列的问题.从CSP器件组装技术、BGA器件的组装技术、0201无源零件组装技术、光电子器件组装技术和无铅焊接技术等方面介绍了电子组装中的复杂技术.     

微电子封装的新进展领域及对SMT的新挑战

介绍了几种微电子新型封装材料,如LTCC、AIN、金刚石、AI-Sic和无铅焊接材料等,论述了正在发展中的新型先进封装技术,如WLP、3D和SIP等,并对封装新领域MEMS和MOEMS作了简介.最后,就这些新技术对SMT的新挑战作了些探讨.     

焊料凸点倒装焊技术

介绍了倒芯片面阵式凸点制作、多层陶瓷基板焊盘制作及倒装焊各关键技术 ,并成功地获得了芯片与基板的互连。     

Packaging technology for high performance CMOS server FujitsuGS8900

Advanced packaging technologies for CMOS based high performance Fujitsu Global Server GS8900, released in late 1999, are introduced in this paper. Extending a new standard for technological leadership among large-scale enterprise servers, the GS8900 broke the 2000 MIPS barrier in performance for the first time by taking advantages of Fujitsu advanced 0.18 μm copper wiring process and chip/MCM/system packaging capabilities, delivering a doubled performance in comparison to its predecessor. The packaging technologies are uniquely characterized in several aspects. First, the high density stacked via type MCM-D technology features four pairs of CPU tightly coupled multiprocessor and large capacity second caches, the maximum processor terminal count is more than 10,000. The processors are wired onto a multilayer thin film MCM substrate with 153 μm pitch high-density area array lead-free bumps. Secondly, maximum four CPU-MCMs, including 16 CPU processors, and 64 GB main memory modules are mounted on one multilayer system board of high frequency transmission properties. Each MCM is held through a high-density ZIF connector of around 3000 I/Os in a 1.27 mm pitch full matrix, which is assembled on the system board with lead-free solders. Thirdly, advanced cooling technologies are developed for improving the system performance and reliability