话音ATM交换的实现——ATM论坛电路仿真系列建议

近年来，随着ＡＴＭ主干网络的建设和发展，研究ＡＴＭ对现有通信业务的支持方式和适配技术是目前ＡＴＭ技术研究的热点之一。话音ＡＴＭ交换在降低话音通信成本和简化网络操作环境等方面提供了大量的技术手段，并且支持在单一网络环境中的多种综合业务传输。ＡＴＭ论坛制定了电路仿真系列建议，话音ＡＴＭ交换的技术已经基本成熟。文章通过对话音ＡＴＭ交换的实现和优化方面的技术进行分析，并提出一种基于ＮａｔｉｖｅＭｏｄｅＡＴ     

ATM交换系统

异步转移模式（ＡＴＭ）是一种新的交换方式，所采用的信元交换是实现宽带综合业务数字网（Ｂ—ＩＳＤＮ）的关键技术之一，与一般的电路交换及分组交换相比较，有不同的性能和特点。文章介绍了ＡＴＭ交换机的功能、结构、分类等等。     

输入/输出ATM交换机在突发性业务下的性能

本文详尽分析了内部无阻塞输入／输出排队反压型ＡＴＭ交换机在突发性业务下信元丢失、交换机最大吞吐量等性能。输入端口信元的到达过程是ＯＮ－ＯＦＦ突发流，且ＯＮ态以概率ｐ发送信元，ＯＮ－ＯＦＦ长度为Ｐａｒｅｔｏ分布的随机变量；属于同一突发流的信元输往同一个输出端口，不同突发流的信元等概率输往不同的输出端口；输入／输出缓冲器长度有限，交换机加速因子Ｓ任意。本文同时比较了突发长度为周期／几何分布下的交换机性能，其结论对实际设计一输入／输出排队反压型ＡＴＭ交换机具有一定参考意义。     

雷达组网中通信链路监测软件设计

雷达网中通信畅通对雷达网的性能起决定性作用,通信链路状态监测是保证通信链路畅通的前提.文中在介绍雷达组网通信系统原理及构成的基础上,描述了通信链路监测软件的设计方案和Socket通信、探询帧通信协议、链路通断状态判断、链路故障设备定位等关键技术,实现了雷达组网中有线链路、无线链路状态的有效监测及故障诊断.     

实用化的ATM交换机中组播通信的实现

ＡＴＭ是面向连接的技术,实现组播通信／广播通信是ＡＴＭ交换机优越于现有ＳＴＭ交换的重大体现,也是ＡＴＭ技术能否在现有网络基础上普遍应用的关键。在共享缓存型ＡＴＭ交换机冲,组播通信的实现是一项重点和难点,本文介绍我院研制的共享缓存型ＡＴＭ交换机中组播通信的设计与实现方法。     

ATM的基本概念

ＡＴＭ的基本概念谭淑贞１ＡＴＭ利用信元交换为了说明ＡＴＭ的基本原理，首先看图１所示的ＡＴＭ交换、传输概念。图中交换机是ＡＴＭ交换机，它采用了名为“信元”（Ｃｅｌｌ）的固定长信息块（组），并以信元为单位进行交换、传输。图中进入Ｂ－ＩＳＤＮ的信息流是一串...     

非均匀业务下反压型输入/输出排队ATM交换机的性能分析

本文分析了一种内部无阻塞反压型输入／输出排队ＡＴＭ交换机，在非均匀负载输入下的信元丢失、信元延时指标，文中采用一一种Ｇｅｏｍ／ＰＨ／Ｉ／Ｋ排队模型分析输入排队系统仲裁系统的分析采用了一种二维Ｍａｒｋｏｖ过程，结论对设计一种反压型输入／输出排队ＡＴＭ交换机有参考意义。     

具有业务量平滑功能的ATM交换机的性能分析

ＡＴＭ网络支持大量的突发业务源。突发业务量可用间断Ｂｅｒｎｏｕｌｌｉ过程描述。本文采用一种循环算法，分析了ＡＴＭ交换机在既有连续比特流业务量又有突出业务量环境下的信元丢失率和平均延迟。数值分析结果和计算机仿真结果一致表明，具有业务量平滑功能的ＡＴＭ交换机的性能有较大改进，。     

在综合业务数字卫星通信网（ISDSN）中应用ATM的研究

ＡＴＭ是国际上正在进行研究的一个热门课题，但是对ＡＴＭ在卫星通信中的应用研究还不多。由于卫星信道的特殊性。将地面Ｂ－ＩＳＤＮ中采用的ＡＴＭ技术完全照搬到卫星通信应用环境中是不合适的。ＡＴＭ在卫星通信中的不同于在地面Ｂ－ＩＳＤＮ中的情况。本文提出一种新思路，不需专用ＡＴＭ交换机，而是利用卫星通信多点－多点的通信能力来实现业务的综合传输和交换，此外还提出了需研究的课题，并对未来的发展趋势进行了展望。     

使用Radium ATM交换机组建宽带综合信息网

随着我国国民经济信息化进程的不断深入,传统电信业务难以满足社会对信息的要求,对信息形式的需求逐步从听觉（话音）向视觉（文字图像）和计算机数据信息扩展。尤其是因特网的高速发展,多媒体业务的巨大需求,对通信的多样性和服务质量提出了更高的要求。一种以数字技术为基础、多媒体业务为中心、个人服务为特色的支持多业务的ＡＴＭ通信技术已经成熟,并得到了大规模的应用。本文介绍如何用ＲａｄｉｕｍＡＴＭ交换机组建宽带业务信息网。１ＲａｄｉｕｍＡＴＭ交换机的技术优势ＲａｄｉｕｍＡＴＭ交换机具有分组交换的多功能宽带核心平台,紧…     

A high-speed-retry banyan switch architecture for giga-bit-rate BISDN networks

This paper proposes a high-speed ATM switch architecture for handling cell rates of several Gb/s in a broadband communication switching system or cross-connect system. The proposed switch architecture, named the high-speed-retry banyan switch, employs a bufferless banyan network between input and output buffers; a cell is repeatedly transmitted from an input buffer until it can be successfully transmitted to the desired output buffer. A simple cell-retransmission algorithm, is employed as is a ring-arbitration algorithm for cell conflict. They are suitable for FIFO type buffers and bufferless highspeed devices. Good traffic characteristics which are independent of switch size are achieved for an internal speed ratio of only four times the input line speed. A prototype system with the internal speed of 1·2 Gb/s is constructed in order to confirm the basic operation of the high-speed-retry banyan switch. The prototype system, even in its present state, could be used to realize a giga-bit-rate BISDN switching system.     

Dimensioning an ATM switch based on a three-stage Clos interconnection network

ATM (asynchronous transfer mode) is a new technique for transmitting voice, data and video. The performance of atm networks will depend on switch structure. Performance analysis of an atm switch based on a three-stage Clos network is presented. In this paper two types of switches are studied: a switch with input queues in the switching elements and a switch with output queues. This study is at the cell level and intends to dimension the switch. First, the traffic is supposed to be uniform, cells arrive on each input according to a geometric arrival process, they are uniformly directed over all the network outputs. An analytic model is proposed for both input and output queues in the switching elements. A study of the saturation throughput is proposed for input buffer switching elements. This work proves the influence of buffer dimensioning on the different stages of the switch. Dissymmetric switching elements are shown to be better than symmetric ones. A model is then designed for nonuniform traffic patterns and output buffers. Two types of non-uniform traffic are presented: single source to single destination (sssd) and multi-hot spots traffic (mhs). Discrete event simulations are used to validate the different models.     

Sharing memory in banyan-based ATM switches

We study a multistage ATM switch in which shared-memory switching elements are arranged in a banyan topology. By “shared-memory,” we mean that each switching element uses output queueing and shares its local cell buffer memory among all its output ports. We apply a buffer management technique called delayed pushout that was originally designed for multistage ATM switches with hierarchical topologies. Delayed pushout combines a pushout mechanism, for sharing memory efficiently among queues within the same switching element, and a backpressure mechanism, for sharing memory across switch stages. The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a variety of traffic conditions. Of the five schemes we simulate, delayed pushout is the only one that performs well under all load conditions     

Performance Analysis of ATM Replicated Banyan Networks with External Input–Output Queueing

This paper develops an improved analysis of ATM switching architectures adopting a replicated banyan interconnection network provided with dedicated input and output queues, one per switch inlet and outlet. Two different plane selection policies are studied, random choice and alternate sharing, and two different operation modes are considered for the interaction between input and output queues, backpressure and output queue loss. These different internal operations are ranked in terms of traffic performance and the problem of optimal allocation of a given buffer budget between input and output queues is addressed. The analysis, which assumes that the network is loaded by uniform traffic, always provides conservative results whereas known models are less accurate and give optimistic traffic results. Packet delay and loss probability performance is evaluated for the ATM switch and its accuracy is assessed using computer simulation also in comparison with results given by previous models.     

Management and control functions in ATM switching systems

As research has progressed, it has become clear that the main difficulties in ATM pertain to its operational details rather than the concept. And it seems likely that these control issues will be much more complicated and costly for ATM switches when compared with current telephone circuit switches. The asynchronous transfer mode (ATM) is the target switching technique for the future public broadband integrated services digital network (B-ISDN). The purpose of this article is to examine the management and control functions in ATM switching systems implied by current industry standards and agreements on OAM and traffic control. Until now, ATM research in the areas of switch design and traffic control have progressed essentially independently. First, we briefly review the B-ISDN Protocol Reference Model and its representation of the different information flows in ATM. Network management and traffic control principles in ATM, and in particular OAM, are overviewed. With this information as background, we attempt to infer their implications on the functional blocks of an ATM switching system. An example switch architecture model with distributed management and control functions is outlined, and some design issues are discussed     

Buffer sizing in an ATM switch for both ATM and STM traffics

Specific queueing models are derived in order to size the buffers of ATM switching elements in the cases of ATM or STM multiplexed traffic. Buffering is performed either at the outputs or in a central memory for ATM multiplexed traffic; for STM multiplexed traffic, buffers can also be provided at the inputs. The buffer size is chosen in order to ensure a loss probability in the switch smaller than 10^?10. It is shown that the buffer size per output in the case of central queueing is smaller than the buffer size in case of output queueing for both ATM and STM multiplexed traffics. Moreover, for STM multiplexed traffic, buffer sizes are identical for input and output queueing. Lastly, it is pointed out that buffers used for STM multiplexed traffic should be 4 to 20 times larger than the corresponding buffers for ATM multiplexed traffic.     

The Tera project: a hybrid queueing ATM switch architecture for LAN

The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns     

32×32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 μm CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32×32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32×32 switching board to achieve large-scale switching systems such as 256×256 or 1024×1024 switches are discussed     

Practical implementation and packaging technologies for alarge-scale ATM switching system

The practical implementation of a trial large-scale asynchronous transfer mode (ATM) switching system and its packaging technologies are described. The architecture of the ATM switching system is discussed with an emphasis on system scalability. A building block architecture in which switching capacity can be expanded in a modular fashion is introduced. The design of the ATM switching system, including the ATM switch element, is described. The implementation of the VLSIs for the ATM switch which realize a highly modular system is explained. Bit-slice techniques are effectively used to realize a high-speed switch element as a CMOS VLSI chipset. An edge-to-edge orthogonal packaging technique is also presented     

Rerouting network: a high-performance self-routing switch forB-ISDN

A high-performance self-routing switch is proposed for ATM (asynchronous transfer mode) switch systems. Switching performance is enhanced by a rerouting algorithm applied to a particular multistage interconnection algorithm. The interconnection algorithm offers many access points to the output and resolves output contention by layering buffers at each switching stage. The author analyzes switching performance and shows that this switch can be easily engineered to have high throughput and low cell loss probability by increasing the number of switching stages. The author also illustrates that the number of switching stages required for a given cell loss probability shows gradual growth with increasing switch size. Analysis shows that the proposed switch is robust even with respect to nonuniform traffic