一九八五年国际固体电路会议述评(续)

逻辑大规模集成电路 规模大和多样化的门阵电路 在逻辑门阵列领域,正在向着大规模集成和品种多样化的方向发展(表Ⅲ)。CMOS门阵芯片的集成规模已超过二万门。随着门阵电路的大规模集成化,芯片内设置存贮器和测试用电路的门阵电路也日益盛行起来。基本单元结构的构成方法也是多种多样。较为引人注目的方法是采     

一种适于FPGA芯片的SRAM单元及外围电路设计

静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。     

基于InP HBT工艺的宽带非线性传输线梳谱发生器MMIC设计

基于NEDI0.7μmInP HBT工艺,设计了一种宽带非线性传输线梳谱发生器MMIC,输出频率范围覆盖DC-100GHz,最大倍频次数高达60.梳谱发生器由40级非线性传输线单元级联构成,每个非线性单元由高阻微带线以及基极-集电极短接的晶体管组成.在一定功率的正弦波或方波信号驱动条件下,芯片输出端可以得到系列高次脉冲...     

一种T-SCC脉冲发生器的研制

针对传统Marx发生器存在的时间常数大、输出效率低、输出参数单一等问题,提出一种寄生参数动态模型并设计了T-SCC（Two-switches Capacitors Cells）脉冲发生器。本文通过将S2BM（Solid-State Bipolar Marx）电容储能单元的全桥IGBT结构优化为T-SCC储能单元结构,根据高频高压下功率IGBT呈现容性负载的特性,优化了寄生电容充放电公式从而建立新型T-SCC脉冲发生器寄生参数动态模型。实验结果表明新的T-SCC脉冲发生器能输出双极性脉冲电压,提高了系统输出电压和寄生电容充放电速度,达到了脉冲上升沿压缩的目的。     

硅栅CMOS门阵列设计

介绍CMOS门阵列的基本结构和设计方法.设计了门阵列的四管和六管两种阵列单元以及输入/输出的I/O单元结构.说明提高CMOS门阵列IC速度的设计和布线,介绍CMOS门陈列的布线方法,建立各种“与非门”、“或非门”和多种触发器、译码器、暂存器等多种基本电路的接触孔和Al连线的宏单元“Macro Cell”的数据库.最后设计并试制成功400门64引出线和300门48引出线,两种CMOS门阵列集成电路,获得设计试制一次成功.缩短了设计周期、降低掩模版的设计和制造成本,提高设计效率和可靠性.     

一个全集成的CMOS脉冲超宽带发射机

本文给出了一个低功耗、全集成的CMOS脉冲式超宽带发射机电路的设计和流片测试结果,其集成了亚纳秒脉冲发生器、脉冲位置调制(PPM)器和天线驱动电路等,可支持多种调制方式并产生最高达1Gp/s的超宽带脉冲序列.设计采用数字驱动信号上升沿触发的新型反馈结构脉冲发生器,可产生稳定的脉冲信号.通过可调的脉冲宽度和PPM调制步长,设计提供了工艺参数和温度变化的补偿手段.     

适用于数据通路的可编程逻辑器件FDP100K

设计研制了一款适用于数据通路的10万门容量的FPGA器件FDP100K(FDP:FPGA for Data-Path),其主要特点为:可编程逻辑单元结构不同于国际上已有的可编程逻辑单元结构,是一种新颖的基于查询表LUT和多路选择器MUX的混合结构;连线资源结构采用新颖的层次式布线结构,提供高度灵活的布线能力.芯片采用SMIC 0.35 μm CMOS工艺,包含1024个可编程逻辑单元和128个可编程IO单元.芯片配合自主开发的软件系统FDE(FPGA Development Environment)进行测试,结果表明:FDP100K芯片的可编程逻辑单元功能正常;芯片的各种连线资源功能正常;可以准确地实现数据通路型电路和其他类型的电路的功能.     

0.13μm SOI标准单元库抗总剂量辐射的测试验证

基于上海微系统与信息技术研究所0.13 μm抗辐射部分耗尽(PD)绝缘体上硅(SOI)互补金属氧化物半导体(CMOS)工艺标准单元库,设计了一款测试芯片,针对总剂量辐射效应对抗辐射标准单元库的验证方法进行研究.测试芯片主要用于测试标准单元的功能和性能,同时为了满足总剂量辐射测试的试验要求,开发了现场可编程门阵列(FPGA)自动测试平台,用于芯片测试和数据采集工作.试验在模拟空间辐射环境下进行,通过了总剂量150 krad(Si)的辐射测试.测试经过辐射后的芯片,单元功能保持正确,性能变化在10％以内,经过退火处理后,内核(core)电流恢复辐射前的水平.     

基于CMOS模拟电路的高速模糊神经网络设计

本文提出了可构成多规则模糊神经网络的CMOS模拟单元电路,包括:类Gauss型隶属度函数电路,电压求小电路和重心算法去模糊电路.基于这些电路设计了一个两输入/一输出、25条规则的控制系统,并通过非线性函数逼近进行了验证.所有单元均采用SMIC 0.18-μm CMOS数模混合工艺制造,芯片测试结果表明:提出的单元电路结构简单,输出电压偏差小,便于扩展和调节;因而适于实现多规则,自适应调节的高速高精度控制系统.     

业界要闻

国内自行研制最高水平的专用集成电路20万门门阵列母片及其代表品种电路已于近日在无锡微电子科研中心研制成功。 20万门门阵列母片采用0.8微米、单层多晶、双层金属CMOS工艺制作,芯片面积为12.58×12.53mm~2,布线单元173160个,分为1008列,170行。最小的布线单元有8只晶     

A flexible gate array architecture for high-speed and high-densityapplications

A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm² routed density in a 0.5 μm TLM CMOS gate array. Compared to previous 5 V 0.7 μm gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM's feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions     

Design and Application of a 20K Gate Array

This paper describes the design and architecture of a novel VLSI gate array in CMOS technology and its application for a 3-bit error checking and correcting (ECC) unit. The cell rows of the master are arranged without intermediate channels for routing (``sea of gates'). This scheme can be utilized to build large macro cells and functional blocks like data paths or systolic array cells which are very area consuming to realize in conventional gate arrays. In addition, special pull-up/pull-down cells are included on the chip which can be used for data buses and timing circuits. The technology used is an advanced p-well CMOS process with 1.8-μm geometric channel lengths and a two-layer metallization. There are 260 programmable pads for input/output functions and 20 additional power pads (280 pads in total). Depending on the logic, circuits with up to 25 000 gates can be realized with this device.     

Design methodology of a 1.2-µm double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-µm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

Design methodology of a 1.2-/spl mu/m double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-/spl mu/m gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

Logic self-electrooptic effect devices: quantum-well optoelectronicmultiport logic gates, multiplexers, demultiplexers, and shift registers

Two-dimensional arrays of logic self-electrooptic effect devices (L-SEEDs), consisting of electrically connected quantum-well p-i-n diode detectors and modulators are demonstrated. The topology of the electrical connections between the detectors is equivalent to the connections between transistors in CMOS circuits. Three different L-SEED arrays were built and tested. Each element in one array can implement any of the four basic Boolean logic functions (i.e., NOR, NAND, AND, OR). Each element in the second L-SEED array can implement the function E=AB+CD. The third L-SEED array consists of 32×16 arrays of symmetric SEEDs (S-SEEDs) connected with optoelectronic transmission gates. Photonic switching nodes, multiplexers, demultiplexers, and shift registers have been demonstrated using this array     

基于光学数字计算空间振幅编码图形法的光学并行阵列逻辑

本文给出了执行光学并行阵列逻辑的一种新的空间振幅编码图形法的原理和特性。为了设计高速并行复合运算,本文还给出了系统的算法,并澄清了AND和OR阵列门的物理意义。也给出了在8f相干光学处理系统中执行的16种复合逻辑运算的结果。     

A subnanosecond 8K-gate CMOS/SOS gate array

An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained. Typical delay times of inverter, two-input NAND, and two-input NOR gates are 0.67, 0.87, and 0.99 ns, respectively, under a typical loading condition (three fan outs and 2 mm first metal). It is shown that ECL speed with CMOS power can be achieved in a system by using the CMOS/SOS gate array. Advantages of the SOS device on speed performance are also discussed.     

An efficient scaling procedure for domain CMOS logic

The layout area required by a domino CMOS gate to support a specific response-time performance for a particular capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI domino CMOS gates. The procedure is equally applicable to other forms of dynamics logic     

Matching the Transconductance Characteristics of CMOS ISFET Arrays by Removing Trapped Charge

This paper presents an approach for matching the transconductance characteristics of CMOS ISFET arrays by removing trapped charge. We describe how to design arrays of floating-gate ISFETs so that ultraviolet (UV) radiation and bulk-substrate biasing can be used to remove the random amount of trapped charge that accumulates on the gates during fabrication. The approach is applied directly to a prototype single-chip 2 2 array of ISFETs, which is designed and fabricated in a standard 0.35- CMOS process. By considering the transconductance characteristics of the 2 2 array before and after UV exposure, it is shown that the response can be matched after 10 h and that the ISFET threshold voltages converge to an equilibrium value of approximately 1 V. After matching, it is found that the ISFET array has a measured sensitivity of 46 mV/pH and can successfully image a change in the pH of a homogeneous electrolyte solution.     

Optoelectronic parallel processing with surface-emitting lasers andfree-space interconnects

Parallel optoelectronic processing that uses smart pixel arrays and free space interconnections may provide an attractive alternative to applications that exhibit a large degree of functional parallelism and require massive input/output data rates. Two fine-grain parallel architectures based on two-dimensional arrays of processing elements are discussed in this paper. The logic complexity of the smart pixels ranges from two-input AND and XOR gates for a database filter to multiple-input multiple-output compare-and-exchange modules for a recirculating bitonic sorting unit. Both systems use vertical-cavity surface-emitting lasers as light sources but light detection and logic are implemented differently. The data filter uses GaAs-based phototransistors while the sorting unit requires silicon detectors and CMOS circuitry for its more complex logic. The free-space one-to-one interconnection patterns required between processing planes can be realized with either refractive or diffractive optics and their simplicity and regularity permit easy scale-up