JPEG2000中高速Tier1编码器的VLSI设计

提出并实现了一种用于JPEG2000编码芯片中高速Tier1编码器的并行流水结构。该编码器采用了双位平面并行编码、通道扫描的流水控制、状态变量实时产生电路以及列内并行上下文生成等技术,实现了一种0状态存储器的多并行流水位平面编码器;并行同步流水的多记号输入算术编码器以及不定算术编码周期下的多输入同步读取电路,使算术编码速度平均为1.3上下文编码记号对/时钟;对算术编码产生的压缩码流存储呈高效的宏流水线结构。该编码器在100MHz工作时钟下,最高编码速度为85M小波系数/s。用SMIC0.25μm工艺库综合时,门电路为6.3万门,片上存储器为26kb(码块大小32×32),关键路径为5.2ns。     

基于率失真优化的递进UTCQ编码

本文提出了一种基于UTCQ量化器的递进静态图像小波编码算法。一致网格编码量化(UTCQ)用于小波系数的量化并得到了非常好的量化效果。UTCQ超集索引值构成系数位平面,率失真优化按照率失真斜率递减的顺序从系数位平面选择编码系数位。最先编码的位具有最大的率失真斜率,每编码一位都会使失真减少最大。率失真斜率的计算仅仅是利用MQ自适应算术编码器的概率状态估计表而进行的查表过程。MQ算术编码器进一步压缩率失真优化选择的系数位。率失真门限方法的编码速度比搜索最大的率失真斜率更快。该算法有较快的编码速度以及好的压缩效果。     

JPEG2000全通道并行EBCOT-Tier1编码器结构设计

新一代静止图像压缩标准JPEG2000采用了EBCOT算法。该算法Tier1部分在上下文生成过程中需要对位平面进行多次通道扫描,效率很低,难以满足高质量图像实时压缩的要求。目前已有多种改进方案被相继提出,主要基于PS/GOCS和多窗口通道并行扫描。该文设计出一种适用于硬件实现的单窗口全通道并行编码结构,目前已通过FPGA验证。实验表明,该结构下Tier1编码速度明显优于现有几种优化方案。同时,本设计所采用的编码逻辑在解码过程中亦可使用,便于进行编解码复用设计。     

JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构

针对JPEG2000硬件实现中小波变换与编码之间占用大量存储的问题,该文提出一种基于码块的存储方案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制,从面积和功耗两方面减小了硬件实现的开销。在实现中,采用基于行的提升变换结构和比特平面并行的编码方式,提高了效率,确保整个过程的实时处理。实验结果表明:在实时编码要求下,对分辨率为512512的图像分片进行四级9/7或者5/3小波分解,码块大小为3232,采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少80%以上。整个结构已通过FPGA验证,且系统时钟可以工作在100MHz。     

高速PCM、图像数据存储器

为了准确接收和存储某遥测系统的PCM、图像数据,设计了基于FPGA的高速PCM、图像数据采集存储器。存储器以FPGA为控制核心,并利用三星FLASH芯片K9WBG08U1M的交叉双平面页编程技术提高数据写入速度;为了实现存储器的多次上电存储并保证上一次上电存储的数据不被覆盖,我们在FPGA控制FLASH实现边擦边写的基础上开发了断电续存技术。设计的存储器具有数据写入速度快、可多次上电存储和抗干扰能力强等特点。     

改进SPIHT算法对医学图像的压缩

医学图像是医学诊断和疾病治疗的重要根据。为了实现图像的存储和远程医疗中快速传输图像的要求,必须对图像进行压缩。先分析CT医学图像经过小波变换后系数的统计特性,在基于小波变换的基础上,用SPIHT算法对CT医学图像进行压缩编码。提出了2种针对CT医学图像压缩编码改进的SPIHT算法。一是细化扫描产生的有效值,二是将小波变换后系数的低频近似部分按二进比特进行传输。用Matlab进行仿真,仿真结果表明改善了峰值信噪比。     

基于ATmage8的打铃器设计

本文介绍了一种由ATmega8单片机和Ds1302万年历时钟芯片构成的新型打铃器.对打铃器的硬件构成、工作原理和软件的编程进行了详细地阐述.系统以DS1302为基准时钟,该器件内含SPI总线接口,可以方便的与ATmega8进行连接.ATmega8片内有512字节的EEPROM存储器,可以存储多组打铃数据.4位LED数码...     

提升小波变换与分形结合的图像压缩算法

遥感图像在环境监测、军事侦察等多方面有着广泛应用,然而遥感图像包含信息量大,对其进行压缩来提高存储效率具有重要意义.传统分形编码由于压缩比大的特点被广泛应用到遥感图像压缩中,但是传统分形编码存在压缩时间太长的问题.提出提升小波变换与改进分形结合的压缩方法,把提升小波变换后的低频分量进行基于最小方差搜索法的分形压缩.实验结果表明,提升小波变换与改进的分形结合的压缩方法与小波变换与分形结合的压缩方法相比,在峰值信噪比保持在35 dB不变的情况下,压缩时间大约可以缩短8倍,图像压缩比也有提高.     

基于人眼视觉特性加权的率失真优化编码算法

本文提出了一种基于人眼视觉特性加权的率失真优化的嵌入式静态图像编码算法。率失真优化是按照率失真斜率递减的顺序编码系数位,最先编码的位具有最大的率失真斜率,每编码一位都会使失真减少最大。率失真斜率的计算仅仅是利用MQ自适应算术编码器的概率状态估计表而进行的查表过程,率失真门限方法的编码速度比搜索最大的率失真斜率更快。基于人眼视觉特性的加权因子改变编码位序而不是编码值,该算法有更快的编码速度以及较好的压缩效果。     

基于P89C51RD2单片机系统远程程序下载的实现

P89C51RD2芯片特点简介 P89C51RD2是8位80C51单片机的派生产品,它们在完全保留80C51指令系统和硬件结构的大框架外,进行了多方面的加强、扩展、翻新和创新,在最大限度地利用原有的结构的方方面面,可以说做到了淋漓尽致。P89C51RD+将原有的对外部数据和程序存储器的16位寻址机制加以利用,把片上的RAM扩展到1k字节,片上的FLASH EPROM扩展到     

A VLSI architecture of JPEG2000 encoder

This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.     

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated     

A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process

The Block Decoder (BD) which is an indispensable component of the JPEG 2000 image compression standard has the highest computational complexity and determines the speed of the overall decoder system. This paper proposes a high throughput pass parallel BD architecture, which can decode more than one bit per clock cycle. In BD, the dependency between context generation and arithmetic decoding unit incorporates stalling and reduces the throughput of the decoding process. The proposed selective byte input and synchronous sample skipping techniques are used to prevent stalling in the decoding process. The proposed architecture achieves 86% more throughput with 50% increment in the hardware cost than that of the best available serial BD architecture. In comparison with the best available pass parallel architecture, throughput improves almost 8.2 times with 61% increment in the hardware cost. Incorporation of the speed up techniques in the design is the main reason for more hardware consumption. The Figure of Merit of the proposed design, which is the ratio of throughput and hardware cost, is more than that of the available BD architectures for typical code block (CB) size of 32 × 32. The ASIC implementation of the proposed design consumes 66 mW power at maximum operating frequency.     

A 212 MPixels/s 4096 $times$ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications

Multiview video coding (MVC) plays an important role in a 3-D video system. In addition, the resolution of HDTV is increasing to present more vivid perception for users. To realize real-time processing of dozens of TOPS, VLSI solution is necessary. However, ultra high computational complexity, a large amount of external memory bandwidth and on-chip SRAM size, and complex MVC prediction structures are three main design challenges of implementation of MVC hardware architecture. In this paper, an MVC single-chip encoder is proposed for H.264/AVC Multiview High Profile and High Profile for 3-D and quad full high definition (QFHD) TV applications, respectively. The 4096 × 2160 p multiview video encoder chip is implemented on a 11.46 mm² die with 90 nm CMOS technology. An eight-stage macroblock pipelined architecture with proposed system scheduling and cache-based prediction core supports real-time processing from one-view 4096 × 2160 p to seven-view 720 p videos. The 212 Mpixels/s throughput is 3.4 to 7.7 times higher than previous work. The 407 Mpixels/W power efficiency is achieved, and 94% on-chip SRAM size and 79% external memory bandwidth are saved by the proposed techniques.     

Dynamic CMOS amplifiers

The method of on-chip CCD clock generation is discussed and successfully demonstrated by a 64 kbit CCD memory. Since the memory chip contains its own CCD clock generator, all inputs are fully TTL compatible. The memory is organized 65 536 X 1 in 256 random access loops of 256 bits each. The memory array employs an 8-phase electrode/bit (E/B approach to achieve high packing density and to increase charge-carrying capacity. The chip size is 7.1 mm X 4.7 mm and 13 percent of the chip area is occupied by the CCD clock generator. The typical power dissipation is 205 mW in the active mode at 1 MHz and 40 mW in the standby mode at 50 kHz. Only 25 percent of the total power is devoted to the CCD clock generation at 1 MHz. The device is processed witlh an n-channel double level polysilicon-gate technology.     

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC     

32×32 shared buffer type ATM switch VLSIs for B-ISDNs

A set of 0.8 μm CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32×32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32×32 switching board to achieve large-scale switching systems such as 256×256 or 1024×1024 switches are discussed