共查询到19条相似文献,搜索用时 93 毫秒
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利用DSP的特点,对大整数的表示进行了全新的定义,由此设计了大整数的基本运算算法-无符号数加法、无符号数减法、无符号数乘法、模P运算、无符号数比较大小、W=(X-Y)mod P的算法、模指数运算W=(X^A)mod P七种运算算法,为用DSP实现数字签名打下了基础。 相似文献
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浮点指数运算是粒子滤波算法中的关键运算之一,在信号处理等诸多领域有着十分重要的应用,通过分析Table-driven算法,给出基于Table-driven算法实现浮点指数运算的硬件结构,并以Verilog HDL进行建模仿真及综合,同时将仿真结果与浮点DSP C6701运算结果进行比较。结果表明基于FPGA的浮点指数运算在保持一定精度的条件下,可以获得更快的运算速度。 相似文献
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卷积运算广泛用于通讯、电子、自动化等领域的线性系统的仿真、分析及数字信号处理等方面.在Matlab中可以使用线性卷积、圆周卷积和快速傅里叶运算实现离散卷积.线性卷积是工程应用的基础,但圆周卷积和快速傅里叶运算实现线性离散卷积具有速度快等优势,圆周卷积采用循环移位,在Matlab中没有专用函数,需要根据圆周卷积的运算过程编制程序代码;快速傅里叶运算(FFT)是DSP的核心算法,在序列比较长时FFT是一种最合适的方法,运算速度快、程序简单,序列越长其优势越明显.以同一个例子介绍了进行离散卷积仿真运算的两种方法与特点. 相似文献
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针对FPGA和ASIC在实现密码算法时的不足之处,本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供,数据通路由可重构单元之间的相互连接实现,异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后,文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中,使用改进的DSDCVS逻辑来设计其运算电路,减小了单元的面积,提高了单元的工作速度。应用实例表明,在实现密码算法时,面向密码算法的异步可重构结构表现出了比FPGA更好的性能。 相似文献
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本文讨论了DSP芯片进行定点运算所涉及的一些基本问题,这些问题包括:数的定标、DSP程序的定点模拟、DSP芯片的定点运算等。这对于理解定点芯片实现DSP算法具有非常重要的作用。 相似文献
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提出一种浮点型数字信号处理器(DSP)硬核结构,在兼容定点数运算的同时,也为浮点数运算提供较好支持。目前各大现场可编程门阵列(FPGA)主流厂商在实现浮点数运算功能时均采用软核实现方式,即将浮点数运算算法映射到芯片上,通过逻辑资源和DSP模块实现。相比于传统方法,提出的硬核结构在不占用FPGA中其他逻辑资源情况下,仅利用DSP模块便能完成浮点数运算。设计中,充分考虑负载和时延影响,插入多级流水线,显著提高浮点数的计算效率。采用中芯国际(MCI)28 nm工艺设计并完成所提出的浮点型DSP硬核结构。仿真结果表明,所提出的硬核结构的单个浮点数加法和乘法效率为0.4 Gflops。 相似文献
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基于DSP+FPGA的高速通用实时信号处理平台设计 总被引:1,自引:1,他引:0
为了数据采集处理设备小型化、智能化和一体化,完成大量数据的采集和实时处理,并通过特殊算法完成复杂运算的目的,本文杓建了一种基于DSP+FPGA的信号处理平台。该平台采用FPGA来实现FFT运算,利用DSP来完成频域信号的分析和处理以及与上位机的通信,应用CPLD来完成整个系统时序控制。该平台主要特点是硬件电路器件具有实时快速的执行速度,并使用了低功耗、低成本的DSP芯片。 相似文献
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高速通用DSP的并行技术 总被引:5,自引:1,他引:4
近年来,通用DSP的发展速度已超过了专用DSP,而且有些DSP的浮点运算能力是专用DSP无法比拟的。文章主要介绍了ADSP-TS101S的性能和特点,并分析了以其作为处理单元构成并行处理系统的优缺点。 相似文献
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De Caro D. Petra N. Strollo A. 《IEEE transactions on circuits and systems. I, Regular papers》2009,56(9):1968-1978
An high-speed special function unit (SFU) is presented in this paper. The system supports the single-precision IEEE-754 floating-point standard and implements faithfully rounded reciprocal, square root, reciprocal square root, logarithm, and exponential functions. The functions are approximated by using a novel constrained piecewise quadratic interpolation technique. In this way, the lookup table size is reduced by 40% with respect to previously proposed techniques, without any loss in accuracy. Error analysis and sizing methodology are presented in the paper. The SFU has been implemented in a 0.18-mum CMOS technology. The circuit is able to operate up to 420-MHz clock frequency, with a power dissipation of 160 mW at 420 MHz. The system can be employed in programmable graphics accelerators and in other applications where high-performance function evaluation is needed. 相似文献
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Focused on the issue that division is com-plex and needs a long latency to compute, a method to design the unit of high-performance Floating-point (FP) divider based on Goldschmidt algorithm was proposed. Bipartite reciprocal tables were adopted to obtain initial value of iteration with area-saving, and parallel multipliers were employed in the iteration unit to reduce latency. FP divider to support pipeline execution with the control of state m achine is presented to increase the throughput. The design was implemented in Digital signal process (DSP) chip by sharing the existed multipliers. 相似文献
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描述了基于TMS320C54x数字信号处理器的TCM语音压缩编码系统。该系统是在TMS320C54xDSP入门套件(DSK,DSP Starter Kit)板上实现,充分发挥了芯片的专用硬件逻辑、专业化的指令以及板上TLC320AC01模拟接口语音处理系统。有效而快速地完成了TCM语音压缩系统的模拟,并给出相应的实验结果。 相似文献
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Logarithmic circuits are useful in many applications that require nonlinear signal compression, such as in speech recognition front-ends (SRFEs) and cochlear implants or bionic ears (BEs). A logarithmic current-input analog-to-digital converter (A/D) with temperature compensation and automatic offset calibration is presented in this paper. It employs a diode to compute the logarithm, a wide linear range transconductor to perform voltage-to-current conversion, and a dual-slope auto- zeroing topology with 60 dB of dynamic range for sampling the envelope of speech signals. The temperature dependence of the logarithm inherent in a diode implementation is automatically cancelled in our circuit topology. Experimental results from a 1.5-/spl mu/m 3-V BiCMOS process show that the converter achieves a temperature stability lower than 150 ppm//spl deg/C from 12/spl deg/C to 42/spl deg/C, and consumes only 3 /spl mu/W of power when sampling at 300 Hz. At this level of power consumption, we show that the design is thermal-noise limited to 8 bits of precision. This level of precision is more than adequate for deaf patients and for speech recognition front-ends. The power consumption is almost two orders of magnitude lower than state-of-the-art DSP implementations, and the use of a local feedback topology achieves a 2.5-bit improvement over conventional dual-slope designs. 相似文献
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相量测量装置的测量单元直接影响装置测量的有效性和准确性。以DSP芯片为主处理器设计了相量测量装置的测量单元。该单元采用离散傅里叶变换相量测量算法,通过设计相关硬件电路和软件实现,可以将电网信号直接引入,每个基波周期将三相相量的正序、负序、零序分解向量经由DSP的SPI模块传给上层数据处理中心。经实际测试,该单元可以实现对线路相量的实时测量,具有较高测量精度,可以准确地跟踪频率变化,满足电力系统稳定监控的要求。 相似文献
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Increasing mask costs and decreasing feature sizes together with productivity demand have led to the trend of platform design. Software programmable embedded cores are used to provide the necessary flexibility in integrated systems. Facing increasing system complexity, single-issue digital signal processors (DSPs) have been replaced by cores providing the execution of several instructions in parallel. The most common programming model for multi-issue DSP core architectures is Very Long Instruction Word (VLIW) which is based on static scheduling, and enables minimization of the worst case execution time and reduces core complexity. The drawback of traditional VLIW is poor code density, which leads to high program memory requirements and, therefore, requires a large silicon area of the DSP subsystem. To overcome this problem without limiting the core performance, a scalable long instruction word (xLIW) is introduced. A special align unit is used for implementing the xLIW program memory interface. In this paper, the align unit and its main architectural feature, a scalable instruction buffer, is introduced in detail. xLIW is part of a project for a parameterized DSP core. 相似文献