A novel monolithic white LED driver with dual dimming mode

This paper presents a hysteretic-current-control LED driver with the dual dimming mode. This novel monolithic driver includes an output switch and a high-side output current sensing circuit using an external resistor to set the nominal average output current (I_OUTnom). By applying an external control signal to the DIM pin, it can alter flexibly the control mode between the analog (DC) and switching (PWM) dimming. In the DC dimming mode, when the input DC control voltage is adjusted from 0.5 to 2.5 V, the average output current can be changed from 20 to 100 % of the current I_OUTnom. While in the switching dimming mode, the output current is proportional to the duty cycle of the input switching signal and changed from about 0 to 100 % of the current I_OUTnom. The driver circuit has been verified in a 0.5 μm HVCMOS process and the die size is about 1.2 × 1.5 mm². This proposed driver can work in 8–40 V power supply, the maximum average output current is up to 1.0 A.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

A DC–DC buck converter with load-regulation improvement using dual-path-feedback techniques

A DC–DC buck converter using dual-path-feedback techniques is proposed in this paper. The proposed converter is fabricated with TSMC 0.35 μm DPQM CMOS process. The structure of the proposed buck converter includes the voltage-feedback and current-feedback design to improve load regulation and achieve high efficiency. The experimental results show the maximum power efficiency is about 94 %. The load regulation is 6.22 (ppm/mA) when the load current changes from 0 to 300 mA. With a 3.6 V input power supply, the proposed buck converter provides an adjustable power output with a voltage range is from 1 to 3 V precisely.     

Design of an integrated single-input dual-output 3-switch buck converter based on sliding mode control

This paper presents the design, implementation, and testing of a proof-of-concept monolithic single-input dual-output buck converter. The proposed architecture implements an analog hysteretic controller. This avoids the use of extra circuitry to generate a dedicated reference carrier signal to create the pulse-width modulated waveform, thus saving area, and reducing static power consumption. Furthermore, the proposed topology implements only three switches (instead of four switches in conventional solutions), and can save additional silicon area with proper design of the power switches in the voltage regulator. The IC prototype was fabricated in standard 0.5 μm CMOS technology (V_THN = 0.78 V, V_THP = ?0.93 V), operates with a single voltage supply of 1.8 V, generates 1.2 and 0.9 V output-voltage levels, and supplies a maximum total current of 200 mA (100 mA provided by each output), reaching up to 88 % efficiency.     

A transient enhanced DVS DC–DC converter based on state trajectory analysis

Dynamic voltage scaling (DVS) can effectively reduce energy consumption by dynamically varying the supply voltage of the system accordingly to the clock frequency. A new DVS-enabled DC–DC converter is presented in this paper. State trajectory is employed to analyze the transient features of PWM and PFM Buck converters. A novel transient enhancement circuit is designed to improve the transient response of the DVS-enabled Buck converter. To further expand the output voltage range of the converter, a current-starved voltage controlled delay line is proposed in the controller of DC–DC converter to obtain an ultra low voltage of 0.5 V. When the input voltage is 3.3 V, the output voltage of the converter can be dynamically regulated from 0.5 to 2.0 V. The output voltage tracking speed is less than 7.5 μs/V and the recovery speed is 33 μs/A for a load current step from 0.6 to 0.2 A at output voltage of 0.5 V. The chip area is 1.75 mm × 1.33 mm in a 0.18 μm standard CMOS process.     

New zero voltage switching DC converter with flying capacitors

A new soft switching converter is presented for medium power applications. Two full-bridge converters are connected in series at high voltage side in order to limit the voltage stress of power switches at V_in/2. Therefore, power metal–oxide–semiconductor field-effect transistors (MOSFETs) with 600 V voltage rating can be adopted for 1200 V input voltage applications. In order to balance two input split capacitor voltages in every switching cycle, two flying capacitors are connected on the AC side of two full-bridge converters. Phase-shift pulse-width modulation (PS-PWM) is adopted to regulate the output voltage. Based on the resonant behaviour by the output capacitance of MOSFETs and the resonant inductance, active MOSFETs can be turned on under zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. Two full-bridge converters are used in the proposed circuit to share load current and reduce the current stress of passive and active components. The circuit analysis and design example of the prototype circuit are provided in detail and the performance of the proposed converter is verified by the experiments.     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

A multiple-output switched-capacitor DC–DC converter for individual brightness control of RGB LEDs with time-interleaved control and output current regulation

In this paper, an integrated multiple-output switched-capacitor (SC) converter with time-interleaved control and output current regulation is presented. The SC converter can reduce the number of passive components and die areas by using only one flying capacitor and by sharing active devices. The proposed converter has three outputs for individual brightness control of red–green–blue (RGB) LEDs. Each output directly regulates the current due to the V–I characteristics of LEDs, which are sensitive to PVT variations. In the proposed converter, the current-sensing technique is used to control the output current, instead of current-regulation elements (resistors or linear regulators). Additionally, in order to reduce the active area, three outputs share one current-sensing circuit. In order to improve the sensing accuracy, bias current compensation is applied to a current-sensing circuit. The proposed converter has been fabricated with a CMOS 0.13-μm 1P6M CMOS process. The input voltage range of the converter is 2.5–3.3 V, and the switching frequency is 200 kHz. The peak power efficiency reaches 71.8 % at V _IN =2.5 V, I _LED1 = 10 mA, I _LED2 = 18 mA, and I _LED3 = 20 mA. The current variations of individual outputs at different supply voltages are less than 0.89, 0.72, and 0.63 %, respectively.     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

Fast transient DC–DC converter with adaptive compensation zero technique

This letter is to present an adaptive compensation zero circuit to achieve good transient response in current-mode DC–DC buck converter. The proposed structure introduces an adaptive resistance dynamically adjusted according to the different output load conditions, which achieves an adequate system phase margin. A monolithic DC–DC buck converter using the proposed structure was fabricated with 0.35 μm CMOS process. Measurement results show that the transient undershoot/overshoot voltage and the recovery time do not exceed 60 mV and 20 μs for a load current variation from 0 to 1 A.     

A fully on-chip 1-μW capacitor-free low-dropout regulator with adaptive output stage

A fully on-chip 1-μW fast-transient response capacitor-free low-dropout regulator (LDO) using adaptive output stage (AOS) is presented in this paper in standard 0.13-μm CMOS process. The AOS circuit is proposed to deliver extra four times of output current of the operational amplifier at medium to heavy load to extend the bandwidth of the LDO and enhance the slew rate at the gate of the power transistor. And the AOS circuit is shut off at light load to reduce the quiescent current and maintain the stability without requiring area-consuming on-chip capacitor. Meanwhile, the proposed AOS circuit introduces V_OUT offset at medium to heavy load to counteract the V_OUT drop, which is caused by I_LOAD increase. Hence, transient performances of LDO and V_OUT drop between light load and full load are improved significantly with 1.1-μA quiescent current at light load. From the post simulation results, the LDO regulates the output voltage at 0.7 V from a 0.9-V supply voltage with a 100-mA maximum load current. The undershoot, the overshoot and the recovery time of the proposed LDO with I_LOAD switching from 50 μA to 100 mA in 1 μs are about 130 mV, 130 mV and 1.5 μs, respectively. And the V_OUT drop between light load and full load reduces to 0.16 mV.     

Freewheel charge-pump controlled single-inductor multiple-output step-up DC–DC converter

This paper presents a freewheel-charge-pump-controlled design for a single-inductor multiple-output (SIMO) DC–DC Converter. By applying the freewheel-charge-pump-controlled (FCPC) technique, the freewheel switching time is reused, and two extra charge-pump outputs are provided by time recycling, with no cost in time sequences. The converter has two step-up outputs and two charge-pump outputs that can be higher or lower than the input supply. The converter utilizes a 1 μH inductor, 4.7 μF charge-pump capacitors and 33 μF output capacitors at a frequency of 1 MHz. The proposed converter shows low cross-regulation and achieves a maximum loading current of 70 mA. Fabricated in a 0.18-μm CMOS process, the proposed circuit occupies 1.3 × 1.3 mm². Experimental results demonstrate that the converter successfully generates four well-regulated outputs with a single inductor. The supply voltage ranged from 1.6 to 2.5 V and the load regulation performance was 0.08, 0.05, 1.7, and 1.9 mV/mA for V_O1, V_O2, V_O3 and V_O4, respectively.     

Fully integrated 1.2-μA and 13-μA quiescent current LDOs with improved transient response

We introduce two extremely low quiescent current (I _Q ) low-dropout (LDO) voltage regulators. The Low I _Q -LDO (LI _Q -LDO) uses 13 μA of total quiescent current and is designed for a maximum load current of 50 mA. The Micro I _Q -LDO (MI _Q -LDO) uses only 1.2 μA of total quiescent current and is designed for a maximum load current of 5 mA. Detailed pole/zero analysis is performed to aid in the design of the LDOs. Two LHP zeros cancel the two non-dominant poles which extend the bandwidth and improve transient response. Both designs are fully integrated, stabilized with an on-chip capacitive load of 100 pF. In load transient, the total variation in output voltage for LI _Q -LDO and MI _Q -LDO is 1 V and 950 mV, respectively, and the total line transient variation is 668 and 599 mV, respectively. Both designs occupy an area of 0.26 mm² in a 0.5-μm CMOS process. Two process-independent figures of merit are proposed to compare LI _Q -LDO and MI _Q -LDO with other published work.     

Sub 1-V highly-linear low-power class-AB bulk-driven tunable CMOS transconductor

This paper describes the design and realization of a sub 1-V low power class-AB bulk-driven tunable linear transconductor using a 0.18-μm CMOS technology. The proposed transconductor employs a class-AB bulk-driven differential input voltage follower and a passive resistor to achieve highly linear voltage-to-current conversion. Transconductance tuning is achieved by tuning the differential output current of the core transconductor with gain-adjustable current mirrors. With 10.4-μA current consumption from a 0.8-V single power supply voltage, simulation results show that the proposed transconductor achieves the total harmonic distortion (THD) of <?40 dB for a peak differential input voltage range of 800 mV at frequencies up to 10 kHz. The simulated input-referred noise voltage integrated over 10-kHz bandwidth is 100 μV, resulting to an input signal dynamic range of 75 dB for THD <?40 dB. A biquadratic G_m-C filter is designed to demonstrated the performance of the proposed transconductor. At the nominal 10-kHz cut-off frequency, the filter dissipates 34.4 μW from a 0.8-V supply voltage and it achieves an input signal dynamic range of 67.4 dB for the third-order intermodulation distortion of <?40 dB.     

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A V_CM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm² consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.     

A flicker-free CMOS LED driver control circuit for visible light communication enabling concurrent data transmission and dimming control

Recent breakthroughs in solid-state lighting technology have opened the door to a variety of applications using light-emitting diodes (LED’s) for not only illumination, but also optical wireless communication. Low-power CMOS technology enables realization of system-on-chip driver circuits integrating multiple functions to control LED device performance, luminance, and data modulation for “intelligent” visible light networking. This paper presents an LED driver circuit architecture, incorporating analog and digital circuit blocks to deliver concurrent dimming control, and data transmission. This is achieved by independent control of output voltage and current using buck converter and current control loops, respectively. This integrated system incorporates the feedback mechanisms to provide uniform light output together with the peak current control, which also prevents flickering. The proposed architecture is flexible enough to take any digital base band modulation format. Designed and implemented in a 180 nm CMOS process, it provides linear 10–90 % dimming control while transmitting data. It also introduces a mechanism which can be applied to the off-the-shelf LED drivers and make them applicable for the visible light communication applications. The power consumption of on-chip circuitry, is negligible compared to the overall power consumption which yields an efficiency of 89 % at 120 mA of load current. The measured bit error rate (BER) varies from 10^?6 at the data rate of 2.5 Mbps to 10^?2 at the data rate of 7 Mbps. All control functions integrated on-chip with the total power consumption of 5 mW.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

Designing a compact soft-start scheme for voltage-mode DC-DC switching converters

In this paper, a compact soft-start scheme is proposed and successfully applied to typical voltage-mode DC-DC switching converters. The adaptive current limitation implemented through DAC control will largely reduce the overshoot voltage under a wide range of output current. Proven experimentally by a buck converter implemented in a 0.5 μm CMOS technology, the post-simulation results show that when the converter starts up, the maximum overshoot (2.7% at I_LOAD=0 A) by the proposed soft-start scheme is less than that with the conventional scheme by 5% under the same condition. The start-up time can be adaptively adjustable depending on load current and the maximum start-up time is around 760 μs with 22 μF output capacitor. The circuits which realize the soft-start scheme can also be fully integrated into the control chip of DC-DC switching converter resulting in low cost.