数字电视多路流复用中PCR抖动的消除

主要根据数字电视系统中的音、视频同步机制,阐述了PCR抖动的产生机理,并针对不同系统时钟机制的多路节目复用器给出了不同的消除PCR抖动的设计方案。     

数字电视接收机减小PCR抖动影响的方法

PCR（PROGRAM CLOCK REFERENCE）是MPEG-2标准中统一编码器系统时钟与解码器系统时钟的关键，肩负着同步音视频，调整解码器系统时钟频率的重要作用。PCR的抖动会使视频输出无彩色、音视频不同步、视频静帧、跳帧……从而影响数字电视节目的收看效果。PCR抖动一直都是工程应用中的难点。本文从数字电视接收端出发提出了减小由网络传输，多路复接与再复接引起的多种类型的PCR抖动影响的软件解决方案，具有很好的工程应用价值，并在中央卫星传播中心，四川有线电视网络中心，贵州数字电视网络中心等处广泛应用。     

关于塞入抖动的若干推论

塞入抖动是采用码速调整技术进行同步的数字通信系统中的重要损伤因素。本文对塞入抖动作了进一步研究，总结了有关抖动频谱分析布的一些规律，并以推论的形式给出。这些推论都有严格的数学证明，可以用于塞入抖动分析与去抖动装置的设计之中。     

传输流中PCR的抖动原因及解决方案

本文详细介绍了数字传输流中引入PCR的原因，以及PCR是如何插入和使用，分析了造成PCR抖动的原因，并通过理论解决了现实传输流中的PCR抖动。     

数字电视时钟恢复和减小PCR抖动影响的方法

讨论了MPEG-2标准中PCR字段在数字电视接收系统中的作用和本地时钟的恢复方法,提出了一种基于数字电视芯片PLM3K平台的系统时钟恢复和减小PCR抖动影响的软件解决方案,具有较高的工程应用价值.     

浅谈影响传输网络性能的抖动特性

同步模块是每个系统的心脏，它为系统中的其他每个模块馈送正确的时钟信号，因此，同步模块的设计和实现在传输系统中显得特别重要。为了通过降低发射和接收错误来提高网络效率，必须使系统的各个阶段都要使用的时钟的质量保持一定的等级。抖动是影响同步网络和时钟恶化的重要因素。本文论述了抖动产生的各种原因以及它们对传输网络性能的影响。     

基于FPGA的EoS系统中帧处理的改进与实现

根据ITU-TX.86协议的规定,设计了一种EoS系统,实现了IP数据包在基于SDH的骨干光传输网络中的高速传输。针对现有帧处理方案在帧同步时延和时钟抖动方面存在的问题,提出了改进的快速帧同步机制和时钟提取方案。采用廉价的FPGA硬件编程实现,通过电路综合与时序仿真表明,方案在缩短帧同步时延和消除时钟抖动方面具有较好的效果。     

塞入式调整与指针调整的比较及抖动分析

塞入式调整与指针调整是用在同步数字体系(SDH)传输系统中的技术,文章将对这两种技术的实现原理、各自特点作详细的比较,对其产生的候时抖动进行分析,并给出实现去抖动的方法。     

光同步数字传输网的传输性能分析

本文首先对光同步数字系列技术进行了简单介绍，然后对SDH光同步数字传输网的传输性能进行了分析，重点介绍了系统误码、抖动产生的机理及度量的参数和规范，最后指出了减少误码、抖动的办法。     

基于AD9255的数据采集系统设计与分析

简要介绍AD9255的性能与特点,并结合FPGA设计1个数据采集系统,完成同步接收、数字下变频、FFT以及频谱显示等操作。设计中,着重分析对同步采样有较大影响的异步数据同步接收模块。同时,简要说明Dither技术在AD采样中的应用,并深入探究AD9255的可选片内抖动功能,最后根据实验数据给出该可选片内抖动功能的作用效果。     

Modeling of the synchronization process jitter spectrum with inputjitter

The synchronous residual time stamp (SRTS) is one approach approved for the encoding and transporting of the continuous bit rate (CBR) service clock in ATM Adaptation Layer 1 (AAL1) allowing CBR services to be transported in ATM cells over the B ISDN. It has been shown by the authors and others that the SRTS method generates waiting time jitter analogous to that produced by other synchronization processes such as pulse stuffing synchronization. Modeling of the synchronization process as it applies to the SRTS method requires a time domain approach to produce an exact expression of the jitter. In this paper, we apply a new time domain analysis technique previously developed by the authors to derive the expressions for the jitter spectrum of the synchronization process in the presence of input jitter on the service clock. Furthermore, the particular form taken by the jitter spectrum when the input jitter is sinusoidal is also found. Experiments verifying the synchronization process jitter spectrum, both with and without sinusoidal input jitter, are reported. Confirmation is also provided that it is possible to approximate timing jitter by phase jitter as long as certain frequency-amplitude limits are observed     

保障流媒体时间结构的网络时延分析

流媒体同步对端到端时延和时延抖动提出了确定的要求,而终端抖动缓存一方面能消除时延抖动的影响,一方面却增加了端到端时延,流媒体同步保障对网络时延的要求不明确。论文从概率保障流媒体同步的角度,确定了保障流媒体同步的抖动缓存容量范围,提出了流媒体同步网络保障的充分条件,针对基于Internet VoIP(Voice over IP)业务的实际网络测试结果,给出了应用流媒体同步网络保障充分条件进行同步保障评价的应用实例并验证了其正确性。     

纳秒半导体激光器的时间抖动和触发同步特性

纳秒半导体激光器（LD）的时间抖动和多个LD并联触发的时间同步性是各类超快光电过程及应用中的重要参数。研究了纳秒脉冲LD（包括LD触发电路）的时间抖动特性以及2个LD的触发同步性。结果表明:纳秒LD（包括LD触发电路）的时间抖动与其驱动电路的驱动电压有关,均在亚纳秒量级范围。单只纳秒LD的时间抖动为72 ps,当1个LD驱动电路同时触发2个并联的纳秒LD时,每个纳秒LD的时间抖动增至约200 ps,2个并联纳秒LD的触发时间同步性近300 ps。     

DVB传输流PCR抖动检测的FPGA实现

主要研究利用FPGA实现DVB码流检测的方法,首先介绍PCR抖动的基本原理及其形成原因,接着阐述系统工作流程以及结构.该设计模块由VHDL语言完成,并通过了系统验证.     

Performance comparison of MRC and EGC on a MC-CDMA system with synchronization errors over fading channels

This work derives the average bit error rate (BER) of the uplink and downlink multicarrier code division multiple access (MC-CDMA) systems using maximum ratio combining (MRC) and equal gain combining (EGC) with synchronization errors over fading channels. The derived equation can simultaneously incorporate the parameters of the fading channel and all of the synchronization errors, including frequency offset, carrier phase jitter, and timing jitter. Numerical results indicate that those two combining schemes on the uplink and downlink MC-CDMA systems are degraded by all of the normalized synchronization errors over 10⁻². The comparison outcomes between MRC and EGC reveal that the MRC generally outperforms EGC in the uplink MC-CDMA system. However, EGC achieves better performance when the number of users is small, the normalized synchronization errors are low and the signal to noise ratio (SNR) is high. In the downlink system, EGC mainly outperforms MRC when the SNR and the number of users are gradually increased and the normalized synchronization errors are low. Therefore, the selection of MRC or EGC depends on the SNR, the synchronization errors and the number of users in uplink and downlink MC-CDMA systems.     

The jitter time-stamp approach for clock recovery of real-timevariable bit-rate traffic

When multimedia streams arrive at the receiver, their temporal relationships may be distorted due to jitter. Assuming the media stream is packetized, the jitter is then the packet's arrival time deviation from its expected arrival time. There are various ways to reduce jitter, which include synchronization at the application layer, or synchronization at the asynchronous transfer mode (ATM) adaptation layer (AAL). The new source rate recovery scheme called jitter time-stamp (JTS) provides synchronization at the ATM adaptation layer 2 (AAL2) which is used to carry variable bit-rate traffic such as compressed voice and video. JTS is implemented, and experiments have shown that it is able to recover the source rate     

Performance aspects of reference clock distribution for evolvingdigital networks

Recent reference clock distribution technologies are reviewed. Performance concepts and specification methodologies for synchronization system designs are then summarized. The focus is on the common master-slave synchronization designs, generally consisting of three subsystems: the primary clock supply, the slave clock supply, and the clock distribution system overlaid on the digital network. Network synchronization performance is specified with relative clock frequency stability and accuracy of the corresponding reference clock. An overview is also given of clock and jitter and wander specification methodologies discussed in CCITT     

Jitter in synchronous residual time stamp

This paper presents jitter characteristics of synchronous residual time stamp (SRTS) used in ATM adaptation layer (AAL) type 1. It is pointed out that low frequency jitter appears at the receiver output of SRTS, similar to pulse stuffing synchronization. The jitter waveform in the SRTS is presented together with its Fourier series representation, and the low frequency jitter amplitude is determined. There is a parameter called the residue that plays the same role as the stuffing ratio in pulse stuffing synchronization, where the low frequency jitter amplitude exhibits a peak when the residue is a rational number. It is shown that the jitter waveform and the low frequency jitter amplitude are somewhat different from those obtained by the analog with pulse stuffing synchronization. The dependencies of the low frequency jitter amplitude to some parameters are also considered. It appears that the higher the reference frequency, the smaller the resulting low frequency jitter amplitude. Some numerical examples are given to demonstrate the validity of the analysis     

Distributed source-destination synchronization using inband clockdistribution

This paper presents a new distributed methodology for source destination synchronization for interactive teleconferencing. The method is based on a reference clock, which is synthesized from a distributed global clock. The global clock is generated by periodically exchanging inband synchronization signals with neighboring nodes. The timing jitter achieved with this method can be arbitrarily close to the jitter obtained by the centralized synchronous methods which usually use an out-of-band, hard-wired reference clock. The global clock synchronization algorithm, used in this work, guarantees frequency locking of all the network nodes to the slowest clock in the system. As a result, the slowest clock can be used as an implicit reference clock for source-destination synchronization protocols, such as synchronous frequency encoding technique (SFET) and synchronous residual time stamp (SRTS). This inband synchronization method does not require the explicit knowledge of which clock is actually the slowest in the system. Therefore, if the slowest clock fails, then another clock on a different node will be the slowest, and the nodes will use it as a reference clock for the source-destination synchronization protocol. The existing out-of-band reference clock techniques do not have this strong fault tolerant property