High Performance Wireless Switch Protocol for IEEE 802.11 Wireless Networks

All mobile stations (STAs) in IEEE 802.11 infrastructure wireless local area networks (IWLAN) are coordinated by an access point (AP). Within the 2.4 GHz unlicensed industry, science, and medicine (ISM) band defined in the IEEE 802.11 2.4 GHz physical layer (PHY) specifications, three channels are available for concurrently transferring data packets at the coverage area of an AP. In most of small/medium enterprises or home environments, an AP with one selected channel is sufficient for covering whole service area, but this implies that the radio resources for the remaining two channels are wasted. In order to overcome the drawback, we propose a new and simple media access control (MAC) protocol, named wireless switch protocol (WSP), for increasing the throughput of IEEE 802.11 IWLAN network to support high quality multimedia traffic. This is achieved by allowing any pair of STAs in IWLAN to exchange data packets in one of other idle channels after their handshake with each other in the common channel controlled by AP. Simulation results show that the total network throughput of WSP depends on the time taken by channel switching, and on the ‘Intranet’ and ‘Internet’ traffic distribution, where the Intranet and Internet mean data transmission between STAs in IWLAN and between the STA and wired host, respectively. When all data packets are Intranet traffic and the traffic load is heavy, the ratio of Goodput for the proposed WSP to that of IEEE 802.11 standard approximates 400%. In the worse case of all Internet traffic, the proposed WSP still obtains the similar throughput as that of IEEE 802.11 standard.Jenhui Chen was born on October 12, 1971 in Taipei, Taiwan, Republic of China. He received the Bachelor’s and Ph.D. degree in Computer Science and Information Engineering (CSIE) from Tamkang University in 1998 and 2003, respectively. In the Spring of 2003, he joined the faculty of Computer Science and Information Engineering Department at Chang Gung University and served as the Assistant Professor. He occupies the supervisor of Network Department in the Information Center, Chang Gung University. Dr. Chen once served the reviewer of IEEE Transactions on Wireless Communications, ACM/Kluwer Mobile Networks and Applications (MONET), and Journal of Information Science and Engineering. His main research interests include design, analysis, and implementation of communication and network protocols, wireless networks, milibots, and artificial intelligence. He is a member of ACM and IEEE.Ai-Chun Pang was born in Hsinchu, Taiwan, R.O.C., in 1973. She received the B.S., M.S. and Ph.D. degrees in Computer Science and Information Engineering from National Chiao Tung University (NCTU) in 1996, 1998 and 2002, respectively. She joined the Department of Computer Science and Information Engineering, National Taiwan University (NTU), Taipei, Taiwan, as an Assistant Professor in 2002. Her research interests include design and analysis of personal communications services network, mobile computing, voice over IP, and performance modeling.Shiann-Tsong Sheu received his B.S. degree in Applied Mathematics from National Chung Hsing University in 1990, and obtained his Ph.D. degree in Computer Science from National Tsing Hua University in May of 1995. From 1995 to 2002, he was an Associate Professor at the Department of Electrical Engineering, Tamkang University. Since Feb. 2002, he has become a Professor at the Department of Electrical Engineering, Tamkang University. Dr. Sheu received the outstanding young researcher award by the IEEE Communication Society Asia Pacific Board in 2002. His research interests include next-generation wireless communication, WDM networks and intelligent control algorithms.Hsueh-Wen Tseng received his B.S. degree in electrical engineering from Tamkang University, Taipei country, Taiwan, in 2001 and M.S. degree in electrical engineering from National Taiwan University of Science and Technology, Taipei, Taiwan, in 2003. He is currently pursuing the Ph. D. degree at the Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan. His research interests include design, analysis and implementation of network protocols and wireless communications.     

BER Performance of Wireless BPSK Communication System in Tunnels With and Without Traffic

The bit error rate (BER) performance for high-speed personal communication service in tunnels with and without traffic is investigated. The impulse responses of tunnels for any transmitter–receiver location are computed by shooting and bouncing ray/image techniques. By using the impulse responses of these multipath channels, the BER performance of BPSK (binary phase shift keying) system with phase and timing recovery circuits are calculated. Numerical results have shown that the multipath effect by the vehicles in the tunnel is an important factor for BER performance. In addition, the effect of space diversity techniques and decision feedback equalizer on mitigating the multipath fading is also investigated.Chien-Hung Chen was born in Kaohsiung, Taiwan, Republic of China, on 8 March 1971. He received the MSEE degree from Tamkang University in 1999. He is studying for Ph.D. degree in the Department of Electrical Engineering, Tamkang University. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.Chien-Ching Chiu was born in Taoyuan, Taiwan, Republic of China, on 23 January 1963. He received the BSCE degree from National Chiao Tung University, Hsinchu, Taiwan, in 1985 and MSEE and PhD degrees from National Taiwan University, Taipei, Taiwan, in 1987 and 1991, respectively. From 1987 to1989, he served in the ROC Army Force as a communication officer. In 1992 he joined the faculty of the Department of Electrical Engineering, Tamkang University, where he is now an Professor. He was a visiting scholar at the MIT and University of Illinois, Urbana from 1998 to 1999. His current research interests include microwave imaging, numerical techniques in electromagnetics and indoor wireless communications.Shi-Cheng Hung received the MSEE degree from Tamkang University in 1998. He is now a RF engineer. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.Chien-Hung Lin received the MSEE degree from Tamkang University in 2001. He is now a RF engineer. His current research interests include indoor wireless communications and numerical techniques in electromagnetics.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

Platform-Based MPEG-4 SOC Design for Video Communications

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981-1986), and an Associate Professor (1986-1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT & T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001--2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

A new pipelined analog-to-digital converter using current conveyors

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within −0.4 LSB and 0.4 LSB and INL is within −0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 μm CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm². Sing-Yen Wu received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2005. His current research interests include CMOS pipelined analog-to-digital converters and mixed-signal integrated circuit. Lu-Po Liao received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2003. His current research interests include analog integrated circuit design and mixed-signal integrated circuit design. Chia-Chun Tsai received the Ph.D. degrees in Electrical Engineering from National Taiwan University, Taipei, Taiwan, 1991. From 1989 to 2005, he served at the Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan. Since 2005 he has been with the Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan, where he is a Full Professor. His current research interests include VLSI design automation and mixed-signal IC designs.     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Scheduling for time-division based shared channel allocation for UMTS

The Universal Mobile Telecommunications System (UMTS) adopts the WCDMA technology as the radio access interface to provide variable transmission rate services. There are four classes of connections identified in UMTS, which are the conversational, streaming, interactive, and background connections. To efficiently utilize radio bandwidth, the shared channel approach is proposed to deliver the packets for the interactive and background connections. This paper proposes a “Shared-Channel Assignment and Scheduling” (SCAS) algorithm to periodically allocate shared channels to serve interactive and background connections. We conduct formal mathematical proofs and simulation experiments to investigate the performance of the SCAS algorithm. We formally prove that with SCAS, a shared channel can be fully utilized (i.e., the utilization of a shared channel can be up to 100%) to serve the interactive connections. Our analysis indicates that compared with the previously proposed shared channel allocation and scheduling algorithms, there are less computation and communication overheads introduced in the SCAS algorithm. The results of the simulation experiments indicate that it is preferred to set up the Transmission Time Interval (TTI; that is, the unit of time interval for shared channel allocation) smaller to optimize the performance of the SCAS algorithm, including the shared channel utilization and the average waiting time of a connection before getting transmission service. A preliminary version [11] of this work has been accepted by IEEE Wireless Communications and Networking Conference 2004. This paper is an extension of the proposed algorithm, and simulation and analysis are conducted to investigate the performance of the proposed algorithm. Chai-Hien Gan was born in Malaysia in 1971. He received his BS degree in computer science from Tamkang University in 1994, Taipei County, Taiwan, and both his MS. and Ph.D. degrees in computer science and information engineering from National Taiwan University, Taipei, Taiwan, in 1996 and 2005, respectively. Since March 2005, he has been a Research Assistant Professor in Department of Computer Science, National Chiao Tung University, R.O.C. His current research interests include wireless mesh networks, mobile computing, personal communications services, and wireless Internet. Phone Lin received his BSCSIE degree and Ph.D. degree from National Chiao Tung University, Taiwan, R.O.C. in 1996 and 2001, respectively. From August 2001 to July 2004, he was an Assistant Professor in Department of CSIE and Graduate Institute of Graduate of Networking and Multimedia, National Taiwan University, R.O.C. Since August 2004, he has been an Associate Professor in Department of CSIE and Graduate Institute Graduate of Networking and Multimedia, National Taiwan University, R.O.C. His current research interests include personal communications services, wireless Internet, and performance modeling. Dr. Lin is an Associate Editor for IEEE Transactions on Vehicular Technology, Editor for IEEE Wireless Communications special issue on Mobility and Resource Management and a Guest Editor for ACM/Springer MONET special issue on Wireless Broad Access. He is also an Associate Editorial Member for the WCMC Journal. P. Lin’s email and website addresses are plin@csie.ntu.edu.tw and http://www.csie.ntu.edu.tw/~plin, respectively. Nei-Chiung Perng is presently a Ph.D. student in the Department of Computer Science and Information Engineering, National Taiwan University. He received his Bachelor and Master degrees in the Department of Computer and Information Science, National Chiao Tung University in 1999 and 2001, respectively. His research interests include real-time systems and scheduling algorithms. Tei-Wei Kuo received B.S.E. degree in computer science and information engineering from National Taiwan University in Taipei, Taiwan, in 1986. He received the M.S. and Ph.D. degrees in computer sciences from the University of Texas at Austin in 1990 and 1994, respectively. He is currently a Professor and the Chairman of the Department of Computer Science and Information Engineering of the National Taiwan University, Taiwan, ROC. He was an Associate Professor in the Department of Computer Science and Information Engineering of the National Chung Cheng University, Taiwan, ROC, from August 1994 to July 2000. Dr. Kuo is a senior member of the IEEE computer society. His research interest includes embedded systems, real-time process scheduling, real-time operating systems, and real-time databases. He has over 100 technical papers published or been accepted in international journals and conferences and has a book “Real-Time Database Systems: Architecture and Techniques” published by Kluwer Academic Publishers (ISBN 0-7923-7218-2, USA). He is the Program Co-Chair of IEEE 7th Real-Time Technology and Applications Symposium, 2001, and an associate editor of the Journal of Real-Time Systems since 1998. He is an executive committee member of the IEEE Technical Committee on Real-Time Systems in 2005 and the steering committee chair of IEEE RTCSA’05. Dr. Kuo has consulted for government and industry on problems in various real-time and embedded systems designs. Dr. Kuo received several research awards in Taiwan, including the Distinguished Research Award from the ROC National Science Council in 2003 and the Young Scholar Research Award from Academia Sinica, Taiwan, ROC, in 2001. Ching-Chi Hsu was born in Taipei, Taiwan in 1949. He received his BS degree in physics from National Tsing Hwa. University in 1971, Hsishu, Taiwan, and both his MS. and Ph.D. degrees in computer engineering from EE department of National Taiwan University, Taipei, Taiwan, in 1975 and 1982, respectively. In 1977, he joined the faculty of the Department of Computer Science and Information Engineering at National Taiwan University and became an associate professor in 1982. During the years between 1987 and 2002, he was first engaged as a professor and became the chairman of the department. During his tenure in National Taiwan University, Dr. Hsu was a visiting scholar of Computer Science Department, Stanford University from 1984 to 1985. After serving in National Taiwan University for over 25 years, Dr. Hsu had left and was promoted as the president of Kai Nan University in 2002. Starting from February 2004, Dr. Hsu has been the executive vice president of the Institute for Information Industry in which he is mainly in charge of accelerating the growth of information industry in the whole nation. His research interests include distributed processing of data and knowledge, mobile computing and wireless networks.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Voltage-Mode Universal Biquadratic Filters with One Input and Five Outputs

Four new voltage-mode universal biquadratic filters each with one input terminal and five output terminals are presented. Each of the first two proposed circuits uses four plus-type second-generation current conveyors, two grounded capacitors and five resistors. The third proposed circuit employs two plus-type second-generation current conveyors, one differential voltage current conveyor, two grounded capacitors and five resistors. The fourth proposed circuit employs two multi-output second-generation current conveyors, two grounded capacitors and five resistors. Each of the proposed circuits can realize all the standard filter functions; highpass, bandpass, lowpass, notch and allpass, simultaneously, without changing the passive elements. The proposed circuits enjoy the features of orthogonal controllable of resonance angular frequencies and quality factors, using only grounded capacitors as well as low active and passive sensitivities. Jiun-Wei Horng was born in Tainan, Taiwan, Republic of China, in 1971. He received the B.S. degree in Electronic Engineering from Chung Yuan Christian University, Chung-Li, in 1993, and the Ph.D. degree from National Taiwan University, Taipei, in 1997. From 1997 to 1999, he served as a Second-Lieutenant in China Army Force. From 1999 to 2000, he joined CHROMA ATE INC. where he worked in the area of video pattern generator technologies. From 2000 to 2005, he joined the Department of Electronic Engineering, Chung Yuan Christian University, Chung-Li, Taiwan as an Assistant Professor. Since 2005, he is an Associate Professor. His teaching and research interests are in the areas of Circuits and Systems, Analog and Digital Electronics, Active Filter Design and Current-Mode Signal Processing. Chun-Li Hou was born in Taipei, Taiwan, Republic of China, in 1951. He received the B.S. degree, M.S. degree, and Ph.D. degree in Electrical Engineering from National Taiwan University, Taipei, in 1974, 1976, and 1991, respectively. From 1977 to 1979, he taught as a lecture in Tamkang College. From 1981 to 1991, he taught as a lecture in the department of Electronic Engineering, Chung-Yuan Christian University, Chung, Taiwan. From 1992 until now, he taught there as an Associate Professor. His teaching and research interests are in the areas of Current-Mode Analog Circuit Analysis and Design, Active Network Synthesis Circuit theory and Applications. Chun-Ming Chang obtained his bachelor and master degrees, both in the field of electrical engineering, from National Cheng Kung University, Tainan, Taiwan, R.O. China, and his Ph.D. degree in the field of electronics and computer science from the University of Southampton, U.K. He had been an associate professor in Chung Yuan Christian University in Taiwan from 1985 to 1991, and has been a full professor in the same University since 1991. His research interest is divided by two relative fields, network synthesis before 1991 and analog circuit design after 1991. He had been a chairman of the electrical engineering department in Chung Yuan Christian University from 1995 to 1999. Recently, he was recommended for inclusion in The Contemporary Who's Who of Professionals 2004 Edition, and nominated by the Governing Board of Editors of the American Biographical Institute for the prestigious title MAN OF THE YEAR-2005, and became an Advisor of the ABI's distinguished RESEARCH BOARD OF ADVISORS due to the invention of Analytical Synthesis Method and OTA-Only-Without-C Circuits in the field of analog circuit design. Wen-Yaw Chung was born in Hsin-Chu, Taiwan, R.O.C., 1957. He received the B.S.E.E. and M.S. degrees from Chung Yuan Christian University, Chung Li, Taiwan, in 1979 and 1981 respectively, and the Ph.D. degree in Electrical and Computer Engineering from Mississippi State University, USA, in 1989. Subsequently, he joined the Advanced Microelectronics Division, Institute for Technology Development in Mississippi, where he was involved in the design of a bipolar optical data receiver. In 1990 he worked as a design manager for the Communication Product Division, United Microelectronics Corporation, Hsin-Chu, where he was involved in the design of analog CMOS data communication integrated circuits. Since 1991 he has been an Associate Professor in the Department of Electronic Engineering at Chung Yuan Christian University. His research interests include mixed-signal VLSI design, biomedical IC applications, sensor and actuator interfacing for deep submicron VLSI electronics.