RF螺旋电感参数的提取方法

射频集成电路（RFIC）中电感元件十分重要,其模型是RFIC模拟的关键．在确定电感的电路模型后,要进行正确的设计和优化,还必须知道模型中各元件的参数．文中首先给出了电感结构的嵌入式和非嵌入式电路模型,然后从已知的S参数通过三种途径提取了模型中集总元件参数,并对三种途径提取的元件参数进行了模拟,以便得到提取模型参数的最佳途径．     

RF螺旋电感参数的提取方法

射频集成电路(RFIC)中电感元件十分重要,其模型是RFIC模拟的关键.在确定电感的电路模型后,要进行正确的设计和优化,还必须知道模型中各元件的参数.文中首先给出了电感结构的嵌入式和非嵌入式电路模型,然后从已知的S参数通过三种途径提取了模型中集总元件参数,并对三种途径提取的元件参数进行了模拟,以便得到提取模型参数的最佳途径.     

RF集成电感的设计与寄生效应分析

分析了体硅 CMOS RF集成电路中电感的寄生效应 ,以及版图参数对电感品质因数 Q的影响 ,并通过Matlab程序模拟了在衬底电阻、金属条厚度、氧化层厚度改变时电感品质因数的变化 ,分析了不同应用频率时版图参数在寄生效应中所起的作用 ,得出了几条实用的设计原则并进行了实验验证 ,实验结果与模拟值符合得很好 ,表明此模拟方法与所得结论均可有效地用于指导射频 (RF)集成电路中集成电感的设计     

射频电路中的电感

介绍了几种射频电路中常见的电感形式，给出了其电感值和Q值的计算公式．可用于工程中设计和分析电感．并阐述了几种电感的实际应用。     

硅集成电感元件的分析、设计与优化

利用采用FDTD(finite-difference time-domain method)方法的计算软件ISE-EMLAB对片上集成电感进行了模拟,并分析了电感的金属宽度、金属间隔、线圈外直径、线圈匝数等设计参数对电感的品质因数、电感值、电阻值等参数的频率特性的影响,进而提出了一种应用于片上集成电感的优化设计的方法.     

硅集成电感元件的分析、设计与优化

利用采用FDTD(finite-difference time-domain method)方法的计算软件ISE-EMLAB对片上集成电感进行了模拟,并分析了电感的金属宽度、金属间隔、线圈外直径、线圈匝数等设计参数对电感的品质因数、电感值、电阻值等参数的频率特性的影响,进而提出了一种应用于片上集成电感的优化设计的方法.     

中心抽头差分电感的等效模型和参数提取

提出了中心抽头差分电感的中心抽头等效模型,对其差分应用时的单端和差分阻抗进行推导,利用两端口S参数测试提取出等效电阻值、等效电感值和品质因数.在0.35μm 1P4M射频工艺上设计并实现一个中心抽头的差分叠层电感,使用去嵌入测试的两端口S参数进行模型验证.实验测试结果表明,在自激振荡频率以内等效模型和测试结果非常吻合.     

中心抽头差分电感的等效模型和参数提取

提出了中心抽头差分电感的中心抽头等效模型,对其差分应用时的单端和差分阻抗进行推导,利用两端口S参数测试提取出等效电阻值、等效电感值和品质因数.在0.35μm 1P4M射频工艺上设计并实现一个中心抽头的差分叠层电感,使用去嵌入测试的两端口S参数进行模型验证.实验测试结果表明,在自激振荡频率以内等效模型和测试结果非常吻合.     

砷化镓衬底上螺旋电感的建模和分析

针对砷化镓(GaAs)衬底上螺旋电感提出了一种改进形式的集总参数等效电路模型,该等效电路模型能很好地表征螺旋电感的高频效应.同时,应用电磁场全波分析方法对螺旋电感进行仿真,并分析各参数对电感性能的影响.从得到的散射参数中提取出有效电感、Q值和自谐振频率.基于参数优化方法提取等效电路模型中各元件值,并利用曲线拟合技术给出其相应的闭合表达式.这些表达式可用于射频和微波集成电路的设计,从而提高电路设计的性能和效率.     

硅集成电感元件的分析、设计与优化

利用采用FDTD (finite-difference time-domain method) 方法的计算软件ISE-EMLAB对片上集成电感进行了模拟，并分析了电感的金属宽度、金属间隔、线圈外直径、线圈匝数等设计参数对电感的品质因数、电感值、电阻值等参数的频率特性的影响，进而提出了一种应用于片上集成电感的优化设计的方法.     

应用于无线收发机关端的片上螺旋型电感的研究

这篇文章探讨了在现在的标准工艺条件下集成电感的设计和分析问题,包括片上螺旋型电感的有关版图,损耗机制,模型和参数提取问题,最后以一种被学术界广泛妆受的模拟工具对电感的有关设计进行了模拟,给出了模拟结果,并进行了分析,给出了设计片上电感应遵循的原,有着工艺技术和人们对电感的寄生效应的认识的加深,可以相信片上集成电感在高频电路中的应用将越来越广泛。     

RF circuit design aspects of spiral inductors on silicon

The design and optimization of spiral inductors on silicon substrates, the related layout issues in integrated circuits, and the effect of the inductor-Q an the performance of radio-frequency (RF) building blocks are discussed. Integrated spiral inductors with inductances of 0.5-100 nH and Q's up to 40 are shown to be feasible in very-large-scale-integration silicon technology. Circuit design aspects, such as a minimum inductor area, the cross talk between inductors, and the effect of a substrate contact on the inductor characteristics are addressed. Important RF building blocks, such as a bandpass filter, low-noise amplifier, and voltage-controlled oscillator are shown to benefit substantially from an improved inductor-Q     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

High-performance inductors on plastic substrate

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.     

A lumped scalable model for silicon integrated spiral inductors

A lumped scalable model for spiral inductors in silicon bipolar technology has been developed. The effect of three different cross sections on inductor performance was first investigated by comparing experimental measurements. Using both the results of this analysis and three-dimensional electromagnetic simulation guidelines, several circular inductors were integrated on a radial patterned ground shield for model validation purposes. The model employs a novel equation for series resistance with only one fitting parameter extracted from experimental measurements. All other model elements were related to technological and geometrical data by using rigorous analytical equations. The model was validated using one- and two-port measured performance parameters of 45 integrated inductors, and excellent agreement was found for all considered geometries up to frequencies well above self-resonance.     

Experimental analysis of the effect of metal thickness on the quality factor in integrated spiral inductors for RF ICs

The effect of metal thickness on the quality (Q-) factor of the integrated spiral inductor is investigated in this paper. The inductors with metal thicknesses of 5/spl sim/22.5 /spl mu/m were fabricated on the standard silicon substrate of 1/spl sim/30 /spl Omega//spl middot/cm in resistivity by using thick-metal surface micromachining technology. The fabricated inductors were measured at GHz ranges to extract their major parameters (Q-factor, inductance, and resistance). From the experimental analysis assisted by FEM simulation, we first reported that the metal thickness' effect on the Q-factor strongly depends on the innermost turn diameter of the spiral inductor, so that it is possible to improve Q-factors further by increasing the metal thickness beyond 10 /spl mu/m.     

RF integrated inductor modeling and its application to optimization-based design

In this paper an optimization-based approach for the design of RF integrated inductors is addressed. For the characterisation of the inductor behaviour the double ??-model is used. The use of this model is twofold. On one hand it enables the generation of the inductor characterisation in a few seconds. On the other hand its integration into the optimization procedure is straightforward. For the evaluation of the model element values analytical expressions based on technology parameters as well as on the device geometric characteristics are used. The use of a technology-based methodology for the evaluation of the model parameters grants the adaptability of the model to any technology. The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors. This tool uses a modified genetic algorithm (MGA) optimization procedure, which has proved its validation in previous work. Due to the design parameter constraints nature as well as the topology constraints, discrete variables optimization techniques are used. The accuracy of the results is checked against a non-commercial software.     

Integrated Inductors Modeling for Library Development and Layout Generation

In this work we propose a modification to the conventional lumped equivalent circuit model for integrated inductors. Also the widely used parametric model is modified. The proposed models expand the frequency range where the integrated inductor behavior is accurately predicted. They are useful in developing automatic tools to assist the designers in selecting and automatically laying-out integrated inductors [1]. This work is based on measurements from integrated inductors fabricated in a standard silicon process.     

Design issues for monolithic DC-DC converters

This paper presents various ideas for integrating different components of dc-dc converter on to a silicon chip. These converters are intended to process power levels up to 0.5W. Techniques for integrating capacitors and design issues for MOS transistors are discussed. The most complicated design issue involves inductors. Expressions for trace resistance and inductance estimation of on-chip planar spiral inductor on top metal layer of CMOS process are compared. These inductors have high series resistance due to low metal trace thickness, capacitive coupling with substrate and other metal traces, and eddy current loss. As an alternative, a CMOS compatible three-dimensional (3-D) surface micromachining technology known as plastic deformation magnetic assembly (PDMA) is used to fabricate high quality inductors with small footprints. Experimental results from a monolithic buck converter using this PDMA inductor are presented. A major conclusion of this work is that the 3-D "post-process" technology is more viable than traditional integrated circuit assembly methods for realizing of micro-power converters.