外延迁移技术制作用于光电子单片集成的Si上GaAs／GaAlAsDHLED

描述了在国内首次采用外延迁移技术研制适合于制作光电子集成电路的硅上硬化镓双异质结发光二极管的工艺过程及实验结果。发光器件是在外延迁移以后流片制作的，克服了光子器件的对准问题，可与电子器件大规模集成。     

新型全固源分子束外延技术及其在器件制作中的应用

１．引言外延生长是半导体材料和器件制造的最关键的工艺技术，外延技术的发展与材料及器件的发展互相促进，共同发展。外延生长技术的应用与发展对于提高半导体材料的质量和器件的性能，对于新材料、新器件的开发，对于半导体科学的发展都有重要的意义。反过来，对器件质量和性能的进一步要求又推动人们探索更新、更好的外延技术。外延技术首先从硅外延技术发展起来，进而到化合物半导体外延。１９６２年、１９６３年，氯化物汽相外延法（ＶＰＥ）和液相外延法（ＬＰＥ）相继问世，用这些方法制备的材料广泛应用于制作各种微波及光电子器件…     

GaN HEMT外延材料表征技术研究进展

氮化镓(GaN)作为第三代半导体材料的典型代表,具有高击穿电场强度和高热导率等优异的物理特性,是制作高频微波器件和大功率电力电子器件的理想材料.GaN外延材料的质量决定了高电子迁移率晶体管(HEMT)的性能,不同材料特征的表征需要不同的测量工具和技术,进而呈现器件性能的优劣.综述了GaN HEMT外延材料的表征技术,详细介绍了几种表征技术的应用场景和近年来国内外的相关研究进展,简要总结了外延材料表征技术的发展趋势,为GaN HEMT外延层的材料生长和性能优化提供了反馈和指导.     

用低压MOVPE法进行GaAs的选择外延生长

GaAs的选择生长是一项有前途的技术,它有希望实现制造电子器件和光电器件的单片集成,因此受到了人们更多的注意.这种GaAs的选择生长就是用MOVPE法在表面涂有SiO_2或其它绝缘膜衬底上进行的.常压MOVPE法生长的GaAs外延层厚度很不均匀,不能用来制作器件.而低压MOVPE法生长的GaAs外延展的厚度却很均匀,纯度也很高.     

功率VDMOS器件用硅外延材料研制

文章阐述了硅功率VDMOS器件的基本原理和器件结构,也展现了作为电力电子器件其广阔的应用领域,提出了功率VDMOS器件对硅外延材料的要求和发展方向。依据功率器件对外延片的要求,通过优化外延工艺程序和优化外延工艺参数,消除或减弱了自掺杂对电阻率均匀性的影响,消除了过渡区对厚度均匀性的影响,也较好地控制了外延层中的结构缺陷...     

第四届全国新型半导体功率器件及应用技术研讨会通知北大核心

一、征文范围1.宽禁带(GaN和SiC等)外延材料的结构设计、制备与检测技术;2.功率器件用GaAs和InP外延材料的结构设计、制备与检测技术;3.基于金刚石、石墨烯的功率器件的结构设计、加工与测试技术;4.微波功率器件的结构设计、加工与测试技术;5.电力电子器件的结构设计、加工与测试技术;6.特种高功率半导体器件的结构设计、加工与测试技术;7.功率器件的封装和可靠性技术;8.功率器件的系统集成技术;     

SiC电力电子技术综述

与硅相比,4H-SiC材料具有高功率、耐高温、高频、高集成度、高效率、高抗辐射等优势,是制作电力电子器件的理想材料,近十年以来SiC电力电子器件性能不断提高.回顾了SiC电力电子器件的发展,总结了材料、工艺和器件所面对的技术问题.笔者认为SiC JBS二极管和MOSFET将成为SiC的主流器件,将在今后十年内获得长足的...     

SiC外延衬底研究现状及其应用前景

随着国民经济发展"节能减排"任务的加剧,以及新兴电子系统变化的要求,电子系统对半导体元器件技术提出了高密度、高速度、低功耗、大功率、宽工作温度范围、抗辐射和高可靠等性能的要求。SiC单晶材料作为新兴的三代半导体衬底材料正好满足这些要求,被认为是制备微波器件、高频大功率器件、高压电力电子器件的优良衬底材料。分别介绍了传统Si-C-H体系和高速Si-C-H-Cl体系SiC外延工艺研究现状,同时介绍了新颖的高纯半绝缘SiC外延工艺研究状况。论述了SiC外延衬底在电力电子器件、微波器件等方面的应用,阐述了SiC外延衬底在未来节能减排、经济建设中的重要性。     

基于国产单晶衬底的150 mm 4H-SiC同质外延技术进展

高阻断电压、大功率密度、高转化效率是电力电子器件技术持续追求的目标,基于4H-SiC优异的材料特性,在电力电子器件应用方面具有广阔的发展前景。围绕SiC MOSFET器件对外延材料的需求,介绍了国内外主流的SiC外延设备及国产SiC衬底的发展,并重点介绍了宽禁带半导体电力电子器件国家重点实验室在国产150 mm(6英寸)SiC衬底上的高速外延技术进展。通过关键技术攻关,实现了150 mm SiC外延材料表面缺陷密度≤0.5 cm^-2,BPD缺陷密度≤0.1 cm^-2,片内掺杂浓度不均匀性≤5%,片内厚度不均匀性≤1%。基于自主外延材料,实现了650～1 200 V SiC MOSFET产品商业化以及6.5～15 kV高压SiC MOSFET器件的产品定型。     

失效器件分析

As重掺杂Si片的电阻率可低到10-3 Ω·cm,可用作外延片的衬底材料,对于正向压降低的半导体器件来说,用这类外延片制作器件是最恰当的选择.As重掺杂Sj片在外延时容易产生气相自掺杂,尤其是同型外延时还存在固态外扩散现象,在整个制作器件过程中易产生工艺参数偏差,导致器件性能下降,严重时器件失效,当然衬底材料也可以选用价格较高的背处理工艺Si片,能有效地抑制由于后续加工工艺产生的许多缺陷.对某生产厂生产的一批器件电参数性能下降的原因进行了剖析,分析阐明了以As重掺杂Si片为衬底的外延片中衬底杂质对器件质量的影响.     

Epitaxial lift-off GaAs LEDs to Si for fabrication of opto-electronic integrated circuits

The authors report, for the first time, the successful integration of GaAs LEDs on Si using the epitaxial lift-off technique. LEDs were processed after the transfer and could be aligned to features on the Si substrate. LED contacts were defined on both sides of the thin layer. Operation characteristics similar to those of LEDs grown on GaAs were observed. This realisation holds out interesting prospects in the fabrication of quasi-monolithic opto-electronic integrated circuits.<>     

Monolithic integration of optoelectronic, electronic and passive components in GaAlAs/GaAs multilayers

The monolithic integration of LEDs, detectors, waveguides, resistors and FETs has been demonstrated in GaAlAs/GaAs multilayer structures. The resulting uncommitted optoelectronic integrated circuits have been operated in transmitter, receiver and repeater configurations.     

Practical OEICs based on the monolithic integration of GaAs-InGaPLEDs with commercial GaAs VLSI electronics

Recent advances in the epitaxy-on-electronics (EoE) integration process, which combines commercial GaAs VLSI electronics with conventional epitaxial growth and fabrication to produce complex, monolithic optoelectronic integrated circuits (OEICs), have resulted in improved integrated light-emitting diodes (LEDs), eliminated any impact on the preexisting electronics, and increased the robustness of the integration process. An EoE-integrated OEIC combining a photodetector, electronics, and LED is presented which demonstrates the capability of this technology to now satisfy practical optoelectronic systems requirements     

Direct bonding of GaAs films on silicon circuits by epitaxial liftoff

Epitaxial liftoff has emerged as a viable technique to integrate GaAs with silicon. The technique relies on the separation of a thin epi-GaAs film from its substrate followed by direct bonding of the thin film to a silicon substrate. The silicon substrate has to meet certain planarity and smoothness conditions in order to obtain high quality bonding. Unfortunately, processed silicon IC chips do not satisfy these conditions. In this paper, we report on the results of two different planarization techniques, plasma etch back and chemical-mechanical polishing, to integrate GaAs LEDs with silicon circuits using epitaxial liftoff. 4 by 8 arrays of GaAs LEDs have been integrated with silicon driver circuits using plasma etch back. We also have lifted off areas as large as 500 mm² and bonded them on 5″ device wafers by chemical-mechanical polishing. This can be essential for mass production of optoelectronic devices based on epitaxial liftoff.     

汽车尾灯模拟控制电路设计

随着交通事故量的逐步增加,汽车尾灯控制电路的安全性、可靠性越来越重要。文中通过数字逻辑设计的基本方,法采用6个LED发光二级管,9块集成电路芯片,2个电容和若干电阻,制作了一个汽车尾灯模拟控制电路。实验证明,该系统完全能实现正常运行、左转、右转、临时刹车等4种常用的汽车尾灯状态,且制作简单、成本低廉、节能可靠、有较高实用价值。     

Design and fabrication of AlGaInP LED array with integrated GaAsdecode circuits

A two-dimensional (2-D) AlGaInP light-emitting diode (LED) array with monolithic integration of one-to-four GaAs MESFET decode circuits has been developed as an image source for portable virtual displays. The epitaxial layers of AlGaInP LEDs with light emission at a wavelength of 605 nm were grown on a semi-insulating GaAs substrate by organometallic vapor phase epitaxy. LED arrays consisting of 240 columns and 144 rows for a total of 34560 pixels were then fabricated on such epitaxial wafers. One-to-four GaAs MESFET decode circuits consisting of eight MESFET's for each decode circuit and a total of 768 MESFET's for a 34 K decode array were fabricated on the semi-insulating GaAs substrate with removal of LED epitaxial layers around the periphery of the LED array. LED arrays with the integrated decode circuits provide a great reduction in I/O terminals. The I/O count of the demonstrated 34 K decode LED array is 104, which is much less than 384 for a comparable array without the integrated decode circuits. The pixel pitch of the LED array is 20 μm and each LED pixel has 10×10 μm² emitting area. The output power of LED pixel is 50 nW at an operation current of 50 μA. The address voltages used to activate the column decode circuits are 3 V for high and -3 V for low, while the address voltages used to activate the row decode circuits are 0 V for high and -3 V for low. The operating voltage of the decode LED array ranges from 3 to 5 V, and the total power dissipation of the decode LED array is less than 16 mW     

Active-Matrix Amorphous-Silicon TFTs Arrays at 180$^circhboxC$on Clear Plastic and Glass Substrates for Organic Light-Emitting Displays

An amorphous-silicon thin-film transistor (TFT) process with a 180$^circhboxC$maximum temperature using plasma-enhanced chemical vapor deposition has been developed on both novel clear polymer and glass substrates. The gate leakage current, threshold voltage, mobility, and on/off ratio of the TFTs are comparable with those of standard TFTs on glass with deposition temperature of 300$^circhboxC$–350$^circhboxC$. Active-matrix pixel circuits for organic light-emitting displays (LEDs) on both glass and clear plastic substrates were fabricated with these TFTs. Leakage current in the switching TFT is low enough to allow data storage for video graphics array timings. The pixels provide suitable drive current for bright displays at a modest drive voltage. Test active matrices with integrated polymer LEDs on glass showed good pixel uniformity, behaved electrically as expected for the TFT characteristics, and were as bright as 1500$hboxcd/hboxm^2$.     

For your eye only

A new generation of contact lenses built with very small circuits and LEDs promises bionic eyesight     

大功率数码管驱动电路的优化设计

对大功率数码管（LED）的功耗进行了分析和计算,指出大功率LED不能简单地用七段译码器进行驱动,而必须进行专门设计。以5英寸数码管为例,对其译码驱动电路进行了对比研究,指出在各种驱动电路中,基于数字芯片MC1413的驱动电路是最优设计。设计了实验电路,实验结果验证了理论分析的正确性和所提出方法的可行性。     

Fabrication and Thermal Analysis of Wafer-Level Light-Emitting Diode Packages

Wafer-level packaged light-emitting diodes (LEDs) are useful for the high-power applications such as back light unit and general solid-state lighting due to the compactness and integrated fabrication process. In this letter, wafer-level packaged LEDs with red, green, and blue multichips were fabricated, and the thermal characteristics of wafer-level packaged LEDs with multichips such as thermal resistance and junction temperature are investigated using both serial and matrix measurement methods.