基于 GSVD 的分布式 MIMO 雷达测向算法

针对分布式多输入多输出（multi-input multi-output, MIMO）雷达测向中存在的数据信息提取不充分、运算量偏大等问题，开展了基于广义奇异值分解（generalized singular value decomposition, GSVD）的测向算法研究，以提高低信噪比条件下的角度估计性能。首先，建立了分布式阵列MIMO雷达回波信号的统一化表征模型；其次，将分布式MIMO雷达系统接收阵列数据的多线程GSVD问题转换为一个联合优化问题，运用交替最小二乘（alternating least squares, ALS）技术实现阵列信号流行矩阵的拟合，并引入子空间类算法实现目标角度联合估计；最后，对优化问题增加l1范数约束，避免了每次迭代中进行的奇异值分解运算，降低了算法运算量。仿真实验从角度联合估计、均方误差、运算时间等方面验证了所提算法的有效性。     

Current-Mode Universal Biquadratic Filter with Five Inputs and Two Outputs Using Two Multi-Output CCIIs

A current-mode universal biquadratic filter with five input terminals and two output terminals is presented. The proposed circuit uses two multi-output second generation current conveyors, two grounded capacitors and three resistors. The new circuit offers the following advantages: use of the minimum number of active components, orthogonal controllability of resonance angular frequency and quality factor, use of grounded capacitors and the versatility to synthesize any type of active filter transfer functions.     

An Analysis of the Blockcipher-Based Hash Functions from PGV

Preneel, Govaerts, and Vandewalle (1993) considered the 64 most basic ways to construct a hash function $H{:\;\:}\{0,1\}^{*}\rightarrow \{0,1\}^{n}Preneel, Govaerts, and Vandewalle (1993) considered the 64 most basic ways to construct a hash function H:   {0,1}^*? {0,1}ⁿH{:\;\:}\{0,1\}^{*}\rightarrow \{0,1\}^{n} from a blockcipher E:   {0,1}ⁿ×{0,1}ⁿ? {0,1}ⁿE{:\;\:}\{0,1\}^{n}\times \{0,1\}^{n}\rightarrow \{0,1\}^{n}. They regarded 12 of these 64 schemes as secure, though no proofs or formal claims were given. Here we provide a proof-based treatment of the PGV schemes. We show that, in the ideal-cipher model, the 12 schemes considered secure by PGV really are secure: we give tight upper and lower bounds on their collision resistance. Furthermore, by stepping outside of the Merkle–Damg?rd approach to analysis, we show that an additional 8 of the PGV schemes are just as collision resistant (up to a constant). Nonetheless, we are able to differentiate among the 20 collision-resistant schemes by considering their preimage resistance: only the 12 initial schemes enjoy optimal preimage resistance. Our work demonstrates that proving ideal-cipher-model bounds is a feasible and useful step for understanding the security of blockcipher-based hash-function constructions.     

Proportional Plus Integral Control for Set-Point Regulation of a Class of Nonlinear RLC Circuits

In this paper we identify graph-theoretic conditions which allow us to write a nonlinear RLC circuit as port-Hamiltonian with constant input matrices. We show that under additional monotonicity conditions on the network’s components, the circuit enjoys the property of relative passivity, an extended notion of classical passivity. The property of relative passivity is then used to build simple, yet robust and globally stable, proportional plus integral controllers. This work was partially supported by CONACyT, México.     

A 1.8 V 828 μW 80 dB digital MEMS microphone

A single-package digital MEMS Capacitive Microphone (MCM) system is presented. The system consists of a MCM, which is wire-bonded with its readout interface (RI). The MCM sensor is fabricated using a combination of surface and bulk micromachining, employing diaphragm-stiffening to achieve piston-like diaphragm-movement and attaining required sensitivity with a smaller diaphragm-area. The RI is designed in 0.35 μm CMOS and it consists of a preamplifier (PAMP), a sigma-delta modulator (SDM), integrated biasing and digital control, converting the MCM capacitive variations into a single-bit over-sampled digital bitstream. The PAMP employs a two-terminal bootstrapped source-follower buffer to make the readout insensitive to the MCM parasitics, subsequently feeding a third-order single-loop single-bit modulator running at 2.5 MHz. The electrical measurements of the standalone RI demonstrate 55 dB A-weighted @ 1 Pa SNDR at the analog PAMP output and 80 dB A-weighted dynamic-range at the digital output, which corresponds to a conversion range from 40 to 120 dB SPL. The SNDR for acoustic measurements is 33 dB A-weighted @ 1 Pa, limited by the higher MCM thermal noise floor and reduced sensitivity (−53 dB V @ 1 Pa). The frequency characterization of the system for the complete audio-band demonstrates the effect of the system package towards higher frequencies (>9 kHz), giving rise to Helmholtz resonance, and reduction in sensitivity for low-frequencies (<400 Hz) because of acoustic short-circuiting inside the MCM due to flow-by slots. The complete system consumes 460 μA of total current for a 1.8 V single-supply. The total system dimensions are 4.5 × 2 mm² (excluding the package), demonstrating the viability of a low-area, low-power and high dynamic-range implementation of digital MCM.     

Flexible Frequency-Band Reallocation: Complex Versus Real

This paper discusses a new approach for implementing flexible frequency-band reallocation (FFBR) networks for bentpipe satellite payloads which are based on variable oversampled complex-modulated filter banks (FBs). We consider two alternatives to process real signals using real input/output and complex input/output FFBR networks (or simply real and complex FFBR networks, respectively). It is shown that the real case has a lower overall number of processing units, i.e., adders and multipliers, compared to its complex counterpart. In addition, the real system eliminates the need for two Hilbert transformers, further reducing the arithmetic complexity. An analysis of the computational workload shows that the real case has a smaller rate of increase in the arithmetic complexity with respect to the prototype filter order and number of FB channels. This makes the real case suitable for systems with a large number of users. Furthermore, in the complex case, a high efficiency in FBR comes at the expense of high-order Hilbert transformers; thus, trade-offs are necessary. Finally, the performance of the two alternatives based on the error vector magnitude (EVM) for a 16-quadrature amplitude modulation (QAM) signal is presented.     

HgCdTe Growth on 6 cm × 6 cm CdZnTe Substrates for Large-Format Dual-Band Infrared Focal-Plane Arrays

This paper describes molecular-beam epitaxy growth of mid-wavelength infrared (MWIR) and long-wavelength infrared (LWIR) dual-band device structures on large-area (6 cm × 6 cm) CdZnTe substrates. Wafer-level composition and defect mapping techniques were used to investigate the limiting mechanisms in improving the cutoff wavelength (λ _c) uniformity and reducing the defect density. Structural quality of epitaxial layers was monitored using etch pit density (EPD) measurements at various depths in the epitaxial layers. Finally, 640 × 480, 20-μm-pixel-pitch dual-band focal-plane arrays (FPAs) were fabricated to demonstrate the overall maturity of growth and fabrication processes of epitaxial layers. The MWIR/LWIR dual-band layers, at optimized growth conditions, show a λ _c variation of ±0.15 μm across a 6 cm × 6 cm CdZnTe substrate, a uniform low macrodefect density with an average of 1000 cm⁻², and an average EPD of 1.5 × 10⁵ cm⁻². FPAs fabricated using these layers show band 1 (MWIR) noise equivalent temperature difference (NETD) operability of 99.94% and band 2 (LWIR) NETD operability of 99.2%, which are among the highest reported to date.     

A 1.1 V 6.2 mW,wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5–6 GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below −8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an IF of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 V supply with an active chip area of 0.0856 mm².     

A Canonical Voltage-Controlled VM-APS with a Grounded Capacitor

A new canonical first order voltage-mode all-pass section (VM-APS) employing a single grounded capacitor as the only passive element and two differential voltage current conveyors as the active elements is proposed. The circuit, with its attractive features of resistorless realization, voltage-controlled pole frequency and low impedance voltage output is a novel and unique offering to the field and an addition to the rich literature on the subject. PSPICE simulations are carried out in 0.5 μ CMOS technology to validate the utility of the proposed circuit.     

A 250 MHz 11 bit 22 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 250 MHz of sampling frequency with less than −70 dB of total harmonic distortion corresponding to 11 bits for an input 60.8 MHz sinusoidal amplitude of 1.8 V _pp at a 3 V supply. The total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.8 V step input, and 1.8 V _pp full-scale differential input range are achieved. The circuit dissipates 22 mW with a 3 V power supply.     

Non-Fragile H ∞ Guaranteed Cost Control for a Non-linear Stochastic System with Both Distributed Delays and Input Delays

The problem of non-fragile H _∞ guaranteed cost control for a delay-dependent non-linear stochastic system is considered. Both distributed delays and input delays appear in the system. A delay-dependent stabilization condition is presented in terms of the Lyapunov stability theory and the linear matrix inequality (LMI) technique. Furthermore, a sufficient condition of the existence of non-fragile H _∞ guaranteed cost controller is constructed. Finally, a numerical example is given to demonstrate the effectiveness and the feasibility of the proposed approaches in this paper.     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

A 3 V 110 μW 3.1 ppm/°C curvature-compensated CMOS bandgap reference

This paper presents design of a high-precision curvature-compensated bandgap reference (BGR) circuit implemented in a 0.35 μm CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves the lowest reported temperature coefficient of ~3.1 ppm/°C over a wide temperature range of [?20°C/+100°C] after trimming, a power supply rejection ratio of ?80 dB at 1 kHz and an output noise level of 1.43 μV $ \sqrt {\text{Hz}} $ at 1 kHz. The BGR circuit consumes a very low current of 37 μA at 3 V and works for a power supply down to 1.5 V. The BGR circuit has a die size of 980 μm × 830 μm.     

Distributed address auto configuration protocol for Manet networks

In heterogeneous network environments, the network connections of a multi-homed device may have significant bandwidth differential. For a multi-homed transmission protocol designed for network failure tolerance, such as SCTP, path selection algorithms for data transmission drastically affect performance. This article studies the effect of path bandwidth differential on the performance of retransmission strategies in multi-homing environments. It identifies that fast retransmission on an alternate path may cause receive buffer blocking when path bandwidth differential is significant and the receive buffer is limited. A theoretical model is proposed for selecting retransmission path during the fast retransmission phase, based on receive buffer and path conditions. From these observations and analysis results, this article proposes that path selection strategies for transmitting new data and retransmitted data should be decoupled. A new path selection scheme is proposed and evaluated through SCTP simulations.     

Fourth-Order Complex-Lag PWVD for Multicomponent Signals with Application in ISAR Imaging of Maneuvering Targets

The fourth-order complex-lag polynomial Wigner–Ville distribution (PWVD) is extended to generate a high resolution time–frequency distribution for multicomponent signals in this paper. For signals with polynomial phase up to order four, the interferences between different components are reduced by the convolution in the frequency domain of the complex-lag PWVD. The complex-lag PWVD can achieve optimal energy concentration, and it is used in the inverse synthetic aperture radar (ISAR) imaging of maneuvering targets, where high quality instantaneous ISAR images are obtained. Simulated results demonstrate the effectiveness of the method.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

Evaluation of WiseMAC and extensions on wireless sensor nodes

In the past five years, many energy-efficient medium access protocols for all kinds of wireless networks (WSNs) have been proposed. Some recently developed protocols focus on sensor networks with low traffic requirements are based on so-called preamble sampling or low-power listening. The WiseMAC protocol is one of the first of this kind and still is one of the most energy-efficient MAC protocols for WSNs with low or varying traffic requirements. However, the high energy-efficiency of WiseMAC has shown to come at the cost of a very limited maximum throughput. In this paper, we evaluate the properties and characteristics of a WiseMAC implementation in simulation and on real sensor hardware. We investigate on the energy-consumption of the prototype using state-of-the-art evaluation methodologies. We further propose and examine an enhancement of the protocol designed to improve the traffic-adaptivity of WiseMAC. By conducting both simulation and real-world experiments, we show that the WiseMAC extension achieves a higher maximum throughput at a slightly increased energy cost both in simulation and real-world experiments.     

A 0.6 V 100 KS/s 8–10 b resolution configurable SAR ADC in 0.18 μm CMOS

A resolution configurable ultra-low power SAR ADC in 0.18 μm CMOS process is presented. The proposed ADC has maximum sampling rate of 100 KS/s with configurable resolution from 8 to 10 b and operates at a supply of 0.6 V. Two-stage bootstrapped switch and voltage boosting techniques are introduced to improve the performance of the ADC at low voltage. To reduce the power consumption of the analog components of the ADC, monotonic capacitor switching procedure and fully dynamic comparator are utilized. The implementation of dynamic logic further reduces the power of the digital circuits. Post-layout simulation results show that the proposed SAR ADC consumes 521 nW and achieves an SNDR of 60.54 dB at 10 b mode, resulting in an ultra-low figure-of-merit of 6.0 fJ/conversion-step. The ADC core occupies an active area of only 350 × 280 μm².     

A localized algorithm for bi-connectivity of connected mobile robots

Teams of multiple mobile robots may communicate with each-other using a wireless ad-hoc network. Fault-tolerance in communication can be achieved by making the communication network bi-connected. We present the first localized protocol for constructing a fault-tolerant bi-connected robotic network topology from a connected network, in such a way that the total movement of robots is minimized. The proposed distributed algorithm uses p-hop neighbor information to identify critical head robots that can direct two neighbors to move toward each other and bi-connect their neighborhood. Simulation results show that the total distance of movement of robots decreases significantly (e.g. about 2.5 times for networks with density 10) with our localized algorithm when compared to the existing globalized one. Proposed localized algorithm does not guarantee bi-connectivity, may partition the network, and may even stop at connected but not bi-connected stage. However, our algorithm achieved 100% success on all networks with average degrees ≥10, and over 70% success on sparse networks with average degrees ≥5.