基于VLIW体系结构的多核处理器设计

本文首先论述了超常指令字VLIW和多核处理器体系结构,重点介绍了华威处理器的设计。该处理器是一款基于VLIW和SIMD体系结构的多核微处理器,本文重点对该处理器的体系结构、指令调度和编译优化技术进行了介绍,并给出了采用推断推测技术的优化结果。     

面向具有VLIW结构DSP的汇编级翻译的方法

为了简化不同体系结构间代码迁移工作,提出一种面向具有超长指令字架构的数字信号处理器的汇编级翻译的方法.前端分析将汇编代码中的指令信息同语义映射为机器无关的中间表示.采用路径探测法移除分支指令延迟槽构建指令流图,并重构源程序控制流图.基于各条指令的时间戳分配和指令间的数据依赖关系分析,移动代码和修改时间戳来线性化并行代码.实验证明,该方法能够正确翻译汇编程序.     

基于VLIW DSP的可重定向编译器设计与实现

本文给出了一种基于VLIWDSP的快速移植编译器的方法,详细讨论了Trimaran架构中的关键技术：Elcor、模拟器以及定制目标机指令和操作码,成功移植了基于BWDSP100芯片单簇体系结构的编译器,很大程度上缩短了开发周期。     

用于网格计算的复合代码生成技术研究

网格计算的研究越来越受到关注，但是网格开发的复杂性制约网格技术普遍使用。讨论了用于网格计算的复合代码生成技术。文中首先简要介绍了自行研制的网格计算快速开发工具GBuilder和代码生成技术，然后详细描述了GBuilder中复合代码生成的体系结构。     

多形态构件的代码生成技术

针对软件的变化能力需求,提出支持可变特性的构件模型,可实现具有变化能力的构件;提出多形态构件:开发态、部署态和客户态,将软件的变化能力合理分解到软件生命周期的各个阶段;提出多形态构件的代码生成技术和多重生成原理,研发了代码生成工具,实现了多形态构件的自动生成.实例表明,该工具及所生成的构件能够很好的满足多变的业务需求和个性化需求.     

基于XML代码生成技术的应用研究

代码生成技术作为一种程序自动化技术具有代码生成模板维护和扩展简单、可支持多操作平台并且易于实现等特点,可提高软件开发的效率和质量。文中介绍了一种基于XML的代码生成器的实现框架和关键步骤,并给出了部分软件代码程序。     

面向密码流体系结构的超长指令字可重构研究

可重构密码流体系结构是一种面向密码运算的新型体系结构,但存在着超长指令字(VLIW)代码稀疏和Kernel体积过大的问题。该文以可重构密码流处理架构S-RCCPA为研究平台,通过大量密码算法在S-RCCPA架构上的适配分析,提出了VLIW可重构技术,并设计了Kernel级指令集、VLIW可重构算法及指令可重构单元。实验证明,该技术能够有效提高VLIW的指令密度,同时降低了VLIW的指令宽度,使得整个Kernel体积减小了约33.3%,并将微码存储器的容量由96 kB降为64 kB,有效降低芯片整体面积和系统功耗。     

Matlab平台DSP自动代码生成技术研究

Oral-DSP编程难度大,耗时长的问题,给出了一种综合运用Matlab软件、CodeComposerStudio（CCS）软件及其内嵌工具和连接软件进行自动代码生成的方法。重点研究DM642EVM板的自动代码生成方法,并以边缘检测实验为例,验证自动生成代码的可执行性。实验结果表明,该代码生成方法不仅具有极高的生成效率,而且灵活易用;生成的可执行代码可以在DSP板上顺利运行,并可取得非常好的处理结果。     

基于Stateflow的步进电机模型的代码生成技术研究

基于DSP的传统电机驱动代码的开发周期长、效率低、实现比较复杂。针对这一问题,文章提出利用Mathworks公司研发的Embedded Coder工具箱辅助DSP实现步进电机的代码生成。文章介绍了步进电机结构和串口通信机制,以及Embedded Coder和Stateflow实现步进电机代码和自定义UART通信协议代码的生成方法。本研究通过使用Stateflow设计步进电机代码模型,并利用Embedded Coder工具生成步进电机的执行代码,实现Simulink环境下DSP程序调试与步进电机系统开发。     

Retargetable Code Generation Based on Structural Processor Description

Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approach to achieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to different target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.     

简单高性能微处理器的设计

提高指令级并行度是处理器体系结构发展的重要方向,也是当前计算机组织、计算机结构课程的重要内容之一。为使学生对指令流水线、超标量等技术有更深入的理解和体会,本文介绍了一个简单的具有超标量流水线结构的微处理器模型的设计思想。针对在指令并行执行过程中出现的数据相关冲突,提出了指令相关性检查算法和数据相关性检查算法。论述了如何利用VHDL语言的特点,准确描述硬件的并行性及系统模块的划分,给出了模拟及仿真验证的例子。     

An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures

In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity of the VLIW-TTA structure, remains general for an arbitrary application and instantiation of the TTA processor and is based on the partial scan approach along with the functional test. The test-time analysis, in order to justify our approach and show the superiority over the classical full-scan, has been performed. The results of our strategy are shown in a few examples at the end of the paper.     

一种适用于低功耗超长指令字DSP处理器的硬件循环缓冲设计

提出了用于VLI WDSP处理器的硬件循环缓冲器的设计.该DSP处理器在结构上利用了在信号处理程序中循环经常出现这一特点,专门设计了硬件循环处理模块用来消除因循环跳转造成的流水线等待,以达到循环的零开销处理从而提高DSP的性能.设计过程中为了减小硬件开销,对循环的长度特点进行了分析,把循环分类两类并用不同的方法处理.结果表明循环跳转的处理是在独立模块中操作,没有造成流水线的等待提高了性能,该硬件循环的面积是3 .8 k逻辑门.     

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1∼26.0%. The DSP has been fabricated in the UMC 0.13 μm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 × 3.15 mm² including 160 KB on-chip SRAM.

基于VLIW处理器的高性能数据通道设计及其VLSI实现

本文提出一种新的基于VLIW处理器的层次化数据通道的VLSI结构,通过独特的微码结构,十分方便地得到了具有可配置特征的高速数据通道的控制模型,模型能有效地改善系统扩展所需要的灵活性,适合构建高性能的媒体处理器阵列.运用VHDL语言实现的硬件设计通过了系统仿真.100MHz时钟频率下的最大数据吞吐率可达1.28Gbit/s.     

一种高性能超宽带线性调频信号源

介绍一种VHF／UHF频段高性能超宽带线性调频信号源的设计与实现。首先简要阐述了高性能超宽带线性调频信号源的设计思想，然后依据基带数字产生结合倍频扩展带宽的思路提出了一种超宽带线性调频信号产生方案，并进行了设计实现研究。测试结果表明：按照本文阐述的指导思想和实现方案所设计的超宽带线性调频信号源达到 了相当高的性能。     

定制VLIW结构实现四精度浮点基本函数

本文针对科学应用中基本函数种类多、实现复杂、使用频率低的特点,提出一种定制VLIW结构四精度浮点基本函数协处理器(QPC-Processor).该结构通过显示并行技术挖掘基本函数实现算法的并行性,在同一硬件平台上通过元操作的不同组合来计算多种基本函数.同时,本文还提出基本函数元操作序列到定制VLIW指令的映射算法,指导基本函数的设计.最后,在FPGA平台上进行验证.实验结果表明,相对软件实现,单个QPC-Processor能够取得6倍以上的加速比,而且,QFC-Processor在同一硬件平台上实现多种类型的算法,弥补单一算法的不足,获得较高的硬件资源利用率.     

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi‐standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual‐clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi‐operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance‐area trade‐off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.