共查询到19条相似文献,搜索用时 796 毫秒
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以电路测试基准ISPD98的模型用例及对应的超图为例,阐述了ISPD98电路网表文件格式、超图的压缩存储格式和文件存储格式.提出了一种ISPD98电路网表到超图的转换算法.它读取ISPD98电路网表文件数据,将其映射到超图的压缩存储格式,并存储为指定的超图文件存储格式,从而有效地将电路划分问题转换为超图划分优化问题.实验表明,该转换算法能正确地将ISPD98电路网表转换为超图的文件存储格式,有效地避免了直接在ISPD98电路网表上进行划分,提高了电路划分的效率. 相似文献
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本文基于VLSI划分问题的需要,提出了一种VLSI设计到赋权超图转换算法.该算法解决的关键问题是,它读取和遍历Verilog语言描述的树状结构VLSI设计,将其转换为赋权超图并存储为指定的文件存储格式,从而有效地将VLSI划分问题转换为超图划分优化问题.进而,本文给出了VLSI设计到赋权超图的转换系统(VLSI/Hypergraph Converter,VHC)的处理流程图,并在Windows平台下用C++设计实现了VHC系统.实验及分析表明,该系统能正确地将Verilog语言描述的门级CPU测试用例转换为赋权超图,避免了直接在VLSI线网上进行划分,提高了VLSI划分的效率. 相似文献
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为了使计算系统具有低功耗和容错能力,基于可逆逻辑设计了一种容错的通用移位寄存器。提出了一种新型的容错可逆逻辑门(Parity-Preserving D Flip_flop Gate, PP_DFG),利用它和存在的容错门,完成了寄存器和多路数据选择器的设计。综合上述模块,构建了容错可逆的通用移位寄存器电路,用Verilog 硬件描述语言建模,仿真显示电路逻辑结构正确。同现有电路相比,根据量子代价、延迟和无用输出对其进行性能评估,结果表明该电路不仅具有容错功能,而且性能提高了16%~50%。设计的电路可作为一种重要的存储元件应用于未来的低功耗计算系统。 相似文献
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可靠通信网多总线结构的超图设计法 总被引:3,自引:0,他引:3
本文在处理机数和可靠度给定情况下,先构造出成本最小、连通性最好图即核度最小图;将此图作为一类超图的代表图、救是其中阶数最小及端口数最小的超图的对偶图;最后根据对偶图,作出其对应的成本最小,可靠性最高的多总线结构。 相似文献
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软硬件协同容错电源控制系统的验证 总被引:2,自引:0,他引:2
王平 《微电子学与计算机》2004,21(5):157-159,162
本文对卫星星载软硬件协同电源控制系统容错设计进行了介绍,利用故障注入方法对创新一号小卫星电源控制系统的容错设计进行了验证,通过设计针对容错设计的测试方案,对容错设计进行了全面的测试,保证了容错设计的可靠性。 相似文献
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本文介绍了一种full-2码的虚拟顶点简单图表示法,简化了双容错数据布局判定定理,最优冗余数据布局定理和双容错数据布局的构造.本文还提出了一种基于完全二部图(对应二维奇偶校验码)的完全1-因子分解的双容错数据布局构造方法,可构造高扩展性双容错数据布局BG-HEDP.与B-CODE等同类双容错数据布局相比,BG-HEDP同样具有更新代价最优、高可靠性和低编码/解码复杂度的优点,冗余率接近最优,而扩展性更好. 相似文献
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本文应用一种新型的双线性/前馈差分器(BFD)来设计开关电流(SI)高通梯形滤波器。这种BFD是用本文提出的SI模块,通用差分器(GD)构成的,此GD具有多种差分功能。文中按S域频带变换和Z域带变换分别介绍了两种不同的设计方法,还给出了Chebyshev高通滤波器和椭圆(Elliptic)高通滤波器设计的实例。 相似文献
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在弹载嵌入式软件设计中,需考虑各种故障模式并进行针对性软件容错设计。软件容错设计包含信息容错、时间容错和结构容错。对于实时性系统来说,接口通讯过程中受到干扰等外界因素会出现通讯数据异常的偶发性故障,针对该故障模式,在信息容错的基础上,进一步设计两种软件容错方案,并开展其风险分析。这两种软件容错设计方法的可行性和有效性均在工程实际应用中得到试验验证。 相似文献
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It is shown that Cartesian product (CP) graph-based network methods provide a useful framework for the design of reliable parallel computer systems. Given component networks with prespecified connectivity, more complex networks with known connectivity and terminal reliability can be developed. CP networks provide systematic techniques for developing reliable fault-tolerant routing schemes, even for very complex topological structures. The authors establish the theoretical foundations that relate the connectivity of a CP network, the connectivity of the component networks, and the number of faulty components: present an adaptive generic algorithm that can perform successful point-to-point routing in the presence of faults: synthesize, using the theoretical results, this adaptive fault-tolerant algorithm from algorithms written for the component networks: prove the correctness of the algorithm: and show that the algorithm ensures following an optimal path, in the presence of many faults, with high probability 相似文献
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With the growth of mobile users and the increasing deployment of wireless access network infrastructures, the issue of fault tolerance is becoming an important component of efficient wireless access network design. In this work, we study a survivable hierarchical network design problem. Given the available capacity, connectivity, and reliability at each level, the problem is to minimize overall connection cost for multiple requests such that the capacity, connectivity, and minimum survivability constraints are not violated. Our study is different than earlier research in regard to the coordination of multiple layers of access networks. The connectivity to the core network may be fully or partially dual-homed paths, or may be single-homed paths. Dual-homing schemes spanning to different levels in the network hierarchy are used if the single-homed connectivity is not enough to guarantee the minimum required survivability. We formulate the problem using mixed integer linear programming and prove the complexity class to be NP-hard. We then propose an off-line genetic algorithm based meta-heuristic. Given the complexity of the problem, simulation results demonstrate that the proposed approach is viable in designing fault-tolerant access networks with dual-homing capability. 相似文献
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The hybrid wireless-optical broadband-access network (WOBAN) is a promising architecture for future access networks. Recently, the wireless part of WOBAN has been gaining increasing attention, and early versions are being deployed as municipal access solutions to eliminate the wired drop to every wireless router at customer premises. This architecture saves on network deployment cost because the fiber need not penetrate each end-user, and it extends the reach of emerging optical-access solutions, such as passive optical networks. This paper first presents an architecture and a vision for the WOBAN and articulates why the combination of wireless and optical presents a compelling solution that optimizes the best of both worlds. While this discussion briefly touches upon the business drivers, the main arguments are based on technical and deployment considerations. Consequently, the rest of this paper reviews a variety of relevant research challenges, namely, network setup, network connectivity, and fault-tolerant behavior of the WOBAN. In the network setup, we review the design of a WOBAN where the back end is a wired optical network, the front end is managed by a wireless connectivity, and, in between, the tail ends of the optical part [known as optical network unit (ONU)] communicate directly with wireless base stations (known as ldquogateway routersrdquo). We outline algorithms to optimize the placement of ONUs in a WOBAN and report on a survey that we conducted on the distribution and types of wireless routers in the Wildhorse residential neighborhood of North Davis, CA. Then, we examine the WOBAN's routing properties (network connectivity), discuss the pros and cons of various routing algorithms, and summarize the idea behind fault-tolerant design of such hybrid networks. 相似文献
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在局部连通性的基础上,提出了针对超立方体网络Hn的扩展的局部k-维子立方体连通性概念,证明了具有扩展的局部k-维子立方体连通性的Hn中正确结点问是连通的;提出了超立方体网络Hn中基于扩展局部k-堆子立方体连通性的路由算法。 相似文献
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The aim of this paper is to present an LSI circuit specially designed for fault-tolerant systems. The circuit in question is a self-testing detection processor named PAD (a french acronym meaning self-testing detection processor). The purpose of the circuit is to enable the user to easily design and realize a fault-tolerant system with off-the-shelf ICs. The major part of this paper focuses on the design specifications of the chip which result from a preliminary study of different possible architectures for a fault-tolerant system. 相似文献
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Two tightly coupled multi-computer testbeds, one providing efficient inter-node communications tailored to the application, and the other providing more flexible full connectivity among processors and memories are used to support validation of the design techniques for distributed real-time systems. The testbeds are valuable tools for evaluating, analyzing, and studying the behavior of many algorithms for distributed systems. We have used the testbeds in studying distributed recovery block scheme for handling hardware and software faults. A testbed has also been used to analyze database locking techniques and a fault-tolerant locking protocol for recovery from faults that occur during updating of replicated copies of files in tightly coupled distributed systems. Testbeds can be configured to represent the operating environments and input scenarios more accurately than software simulation. Therefore, testbed-based evaluation provides more accurate results than simulation and yields greater insight into the characteristics and limitations of proposed concepts. This is an important advantage in the complex field of distributed real-time system design evaluation and validation. Therefore, testbed-based experimentation is an effective approach to validate system concepts and design techniques for distributed systems for real-time applications. 相似文献
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Garcia J. Palomo F.R. Luque A. Aracil C. Quero J.M. Carrion D. Gamiz F. Revilla P. Perez-Tinao J. Moreno M. Robles P. Franquelo L.G. 《Industrial Electronics, IEEE Transactions on》2004,51(6):1168-1180
Use of advanced communication technologies, highly integrated control, and programming platforms drastically increases the performance of industrial control systems. That is the case of Motronic, where the synergistic collaboration between industry and academia has led to an advanced distributed network control system. To be commercially successful, it needs to have a low cost and to be robust, even if this requirement implies that it is a custom design and not based on previously existing commercial solutions. Use of standards and off-the-shelf products lower development costs, but usually raise production costs. In this paper, we show that, in certain applications, design of a new system from scratch is more advantageous. This system comprises a set of dynamically reconfigurable local controller nodes, a graphical programming environment, a remote supervision and control system, and a fault-tolerant fiber optical network. TCP/IP connectivity is provided by the use of a local gateway. Motronic is currently being applied in the integrated control of large production plants and in energy and power management industries. 相似文献