Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20 nm with channel thickness values of 10 and 5 nm. Our results reveal that 10 nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off frequency f_T and maximum frequency of oscillations f_max by 80.5%, 18.8%, 83.5% and 81.7%, respectively compared with equivalent GeOI device at L_g =20 nm. Furthermore, such devices exhibit 78.8% increase in ON-current I_ON while yield 44.5% reduction in delay as compared to Ge control devices enabling them attractive for logic applications. Thinning of the channel thickness from 10 to 5 nm increases peak Av, peak transconductance efficiency and reduces output conductance and OFF-current I_OFF while degrading other parameters in all GeSnOI and control Ge devices.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses

We report on the reliability of InGaAs/InP DHBT technology which has applications in very high-speed ICs (over 100 Gbits/s). This work presents the results of accelerated aging tests under thermal and electrical stresses performed on HBT up to 2000 h. Stress conditions consist in applying collector–emitter bias V_CE from 1.3 to 2.7 V and collector current densities J_C of 400 and 610 kA/cm². The corresponding junction temperatures T_J extends from 83 to 137 °C. The base current ideality factor η_B increase and the current gain β decrease have revealed a degradation of the base–emitter junction. The normalized current gain β_norm drop has occurred earlier for higher V_CE and/or higher T_J. A 20% decrease of β_norm chosen as the failure criterion leads to an activation energy of 1.1 eV.     

Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

Modeling of Ga1−xInxAs1−y−zNySbz/GaAs quantum well properties for near-infrared lasers

The aim of this work is to model the properties of GaInAsNSb/GaAs compressively strained structures. Indeed, Ga_1?xIn_xAs_1?y?zN_ySb_z has been found to be a potentially superior material to GaInAsN for long wavelength laser dedicated to optical fiber communications. Furthermore, this material can be grown on GaAs substrate while having a bandgap smaller than that of GaInNAs. The influence of nitrogen and antimony on the bandgap and the transition energy is explored. Also, the effect of these two elements on the optical gain and threshold current density is investigated. For example, a structure composed of one 7.5 nm thick quantum well of material with In=30%, N=3.5%, Sb=1% composition exhibits a threshold current density of 339.8 A/cm² and an emission wavelength of 1.5365 μm (at T=300 K). It can be shown that increasing the concentration of indium to 35% with a concentration of nitrogen and antimony, of 2.5% and 1%, respectively, results in a decrease of the threshold current density down to 253.7 A/cm² for a two well structure. Same structure incorporating five wells shows a threshold current density as low as 221.4 A/cm² for T=300 K, which agrees well with the reported experimental results.     

A low-cost horizontal current bipolar transistor (HCBT) technology for the BiCMOS integration with FinFETs

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region's volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency (f_T) of 21.4 GHz, the maximum frequency of oscillations (f_max) of 32.6 GHz and the collector–emitter breakdown voltage (BV_CEO) of 5.6 V, which are the highest f_T and the highest f_TBV_CEO product among the lateral bipolar transistors (LBTs).     

Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced ΔV_T can be reduced to a quarter of ΔV_T found after the static NBT stress.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

A 24 W Ku band GaN based power amplifier with 9.1 dB linear gain

A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of f_T=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band.     

RF performance enhancement in multi-fin TFETs by scaling inter fin separation

This paper deals with the extraction of RF metrics of multi-fin Tunnel FET (TFET) with the inter fin separation (IFS) scaled up to 1 nm. The structure of multi-fin TFET is designed by varying the number of fins (N) from 1 to 5. As the number of fins increases, the drive current (I_D) gets multiplied and the maximum I_D of 76 µA can be achieved for N = 5. Higher I_D is obtained without compromising the leakage current (I_OFF) which is in the range of femto amperes. For the various values of IFS, RF metrics such as intrinsic gain (A₀), unity gain cut-off frequency (f_t), maximum oscillation frequency (f_max), and admittance (Y) parameters are extracted for multi-fin TFETs. The results show for lesser values of IFS, higher intrinsic gain is obtained and the value does not affect as N increases. The maximum value of f_t and f_max is obtained because of the electrostatic coupling between the two adjacent fins. The Y parameters are extracted at an operating frequency of 10 GHz. It can be seen that Y parameters offer better values as the number of fins and IFS increases. This is due to the larger value of gate to drain capacitance (C_gd) which occurs because of the parasitic effect for higher values of IFS.     

Synthesis and electroluminescent properties of highly efficient anthracene derivatives with bulky side groups

Three new asymmetric light emitting organic compounds were synthesized with diphenylamine or triphenylamine side groups; 10-(3,5-diphenylphenyl)-N,N-diphenylanthracen-9-amine (MADa), 4-(10-(3,5-diphenylphenyl)anthracen-9-yl)-N,N-diphenylaniline (MATa), and 4-(10-(3′,5′-diphenylbiphenyl-4-yl)anthracen-9-yl)-N,N-diphenylaniline (TATa). MATa and TATa had a PL_max at 463 nm in the blue region, and MADa had a PL_max at 498 nm. MADa and MATa had T_g values greater than 120 °C, and TATa had a T_g of 139 °C. EL devices containing the synthesized compounds were fabricated in the configuration: ITO/4,4′,4′′-tris(N-(2-naphthyl)-N-phenyl-amino)-triphenylamine (2-TNATA) (60 nm)/N,N′-bis(naphthalen-1-yl)-N,N′-bis(phenyl)benzidine (NPB) (15 nm)/MADa or MATa or TATa or 9,10-di(2′-naphthyl)anthracene (MADN) (30 nm)/8-hydroxyquinoline aluminum (Alq₃) (30 nm)/LiF (1 nm)/Al (200 nm). The efficiency and color coordinate values (respectively) were 10.3 cd/A and (0.199, 0.152; bluish-green) for the MADa device, 4.67 cd/A and (0.151, 0.177) for the MATa device, and 6.07 cd/A and (0.149, 0.177) for the TATa device. The TATa device had a high external quantum efficiency (EQE) of 6.19%, and its luminance and power efficiencies and life-time were more than twice those of the MADN device.     

Thermal stability of lead-free CH3NH3SnxI3 systems (0.9 ≤ x ≤ 1.1) for photovoltaics

Methylammonium-tin-iodide (MASn_xI₃, 0.9 ≤ x ≤ 1.1) systems were prepared by precipitation process in aqueous solutions. The “as prepared” MASn_xI₃ systems exhibited a tetragonal crystalline phase (space group I4cm) with polyhedral crystallites (length 50–400 µm). The as prepared samples were annealed at T = 150 °C for t = 8 h under nitrogen and synthetic air. Under nitrogen, the CH₃NH₃Sn_xI₃ systems adopt nearly-cubic tetragonal structure (space group P4mm) with crystallites of 2–4 µm length whereas a degradation process with formation of non-crystalline phases occurred in air. The differential thermal analysis (DTA) profile in nitrogen revealed events at T = 247 °C, T = 297 °C (decomposition of CH₃NH₃Sn_xI₃ systems into methylamine (CH₃NH₂), hydroiodic acid (HI) and SnI₂), and in the range T = 342–373 °C (melting of SnI₂) respectively. The thermal profile in air showed endothermic events at T = 139 °C and T = 259 °C with additional events at onset temperatures of T = 337 °C and T = 423 °C respectively which correspond to the formation of Sn(IV)-O binds and to the decomposition of methylamine. Static thermogravimetry analysis (TG), performed at T = 85 °C and T = 150 °C for t = 2 h, revealed a linear weight loss as a function of the time. The optical absorption spectra displayed absorbance edges in near infrared range, at 1107.0 nm (x = 0.9), 1098.6 nm (x = 1.0) and 1073.2 nm (x = 1.1) respectively.     

Impact of the lateral straggle on the Analog and RF performance of TFET

In this work, the effect of the variation in lateral straggle on TFETs performance is demonstrated. The ion implantation technique during fabrication process causes the extension of dopants from source/drain region towards the channel. Even though the use of non-zero tilt angle at the time of ion implantation is necessary to avoid the channeling effect, however, series resistance, threshold voltage roll offs, switching speed and effective channel length of the device get affected by the non abrupt doping profile at the source/drain-body junction. It is established earlier that TFET is very convenient for Analog/RF application owing to its below 60 mV/decade subthreshold swing and reduced short channel effects. In order to show the effect of lateral straggle on TFET’s performance, various Analog figure of merits (FOMs) such as drain current (I_d), transconductance (g_m), transconductance generation factor (g_m/I_d), output resistance (R_o), intrinsic gain (g_mR_o) and RF figure of merits (FOMs) like unity gain cutoff frequency (f_T), transit frequency of maximum available power gain (f_MAX) are investigated for the variation in straggle parameter from 0 nm to 5 nm in order to optimize the device performance. The circuit performance of the device for different lateral straggle is carried out using common source amplifier.     

K Band SiGe HBT single ended active inductors

The study of monolithic integration of active inductors (AI) on a 0.25 μm SiGe BiCMOS technology with 4 metal layers and HBTs with f_T=120 GHz is presented. Two topologies are presented and their performance discussed. Q values higher than 30 were obtained on a 3.4 GHz bandwidth at 28 GHz and maximum values as high as 100. Active inductors can be biased with low power, such as 2 V with a nominal DC current of 0.6 mA. The inductance value is controlled by external bias voltages and adjustments up to 40% were measured. Simple gyrators topologies with only 2 transistors are used for low power consumption and good performance at K Band is proved. The internal parameters of small signal model of HBT were studied and the crucial parameter to enhance the negative resistance and so the Q of the AI was identified.     

Fabrication of a CoSb3-based thermoelectric module

A CoSb₃-based thermoelectric module was fabricated using Ce_0.45Co_2.5Fe_1.5Sb₁₂ p-type leg and Yb_0.25Co₄Sb₁₂/Yb₂O₃ n-type leg. Ag–Cu foil was used to construct the junction of hot side legs. With two p–n couples, the module generated a maximum output power (P_max) of 140 mW and a maximum open-circuit voltage (V_o) of 210 mV under the thermal condition of hot side temperature T_h=810 K and a temperature difference ΔT=490 K. No deterioration in output power in vacuum was seen when thermal cycle of five times for the module was carried out under T_h=810 K and ΔT=490 K with natural cooling to room temperature, which shows the module has high durability.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation

This paper investigates and compares the impacts of metal-gate work-function variation on important analog figures-of-merit (FOMs) for TFET and FinFET devices using 3-D atomistic TCAD simulations. Our study indicates that, at 0.6 V supply voltage and 0.2 V gate-voltage overdrive, TFET exhibits superior variation immunity regarding transconductance to drain–current ratio (g_m/I_DS), output resistance (R_out) and intrinsic gain, and comparable variability in g_m and cutoff frequency (f_T) as compared with the FinFET counterparts. In addition, how the correlations between pertinent parameters (e.g., g_m and R_out) impact the variation immunity of important analog FOMs are analyzed. Our study may provide insights for low-voltage analog design using TFET/FinFET technologies.