Design of low-power hybrid digital pulse width modulator with piecewise calibration scheme

A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm², with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM.     

A VCO-based phase-expanding conversion designed for time-domain data converters

This paper presents the design of a VCO-based phase-expanding converter (PEC) that converts a time residue to improve time resolution for the time-domain data converters. A voltage controlled oscillator, which has multiphase structure, is combined with the multi-layer delay chain to generate quadruple phases, and thus expands the overall resolution. Since the architecture of this converter is flexible for different designs, we propose a 6-bit, 250 MHz PEC using a 16-phase, 1 GHz VCO with quadruple phase expander in this paper. Simulations in a 0.18 μm the CMOS process indicate that the PEC has DNL less than ±0.2 LSB LSB, and INL less than ±0.3 LSB. Furthermore, with the frequency variation from 0.9 GHz to 1.1 GHz, the PEC still has DNL ±0.21 LSB, and INL ±0.29 LSB. Experiment results show that the DNL is 0.52–0.13 LSB and the INL is 0.21–0.66 LSB.     

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.     

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18 μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5 dB with flatness of ±0.4 dB from 5–11 GHz, while maintaining bandwidth of 4.2–12.3 GHz. An input return loss (S₁₁) less than −10.4 dB and output return loss (S₂₂) less than −9.5 dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41 ps and only consuming 17 mW power from 1.2 V supply voltage. A good output 1-dB compression point OP1 dB of 3.7 dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.     

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

As the size of CMOS devices is scaled down to lower the power consumption and space occupied on the chip to the nano-scale, unfortunately, noise is not reduced accordingly. As a result, interference due to noise can significantly affect circuit performance and operation. Since noises are random and dynamic in nature, probabilistic noise-tolerant approaches are more desirable to handle this problem. However, trade-offs between hardware complexity and noise-tolerance are severe design challenges in the probabilistic-based noise-tolerant approaches. In this paper, we proposed a cost-effective common-feedback probabilistic-based noise-tolerant VLSI circuit based on Markov random field (MRF) theory. We proposed a common latch feedback method to lower the hardware complexity. To further enhance the noise-tolerant ability, the common latch feedback technique is combined with Schmitt trigger. To demonstrate the proof-of-concept design, a 16-bit carry-lookahead adder was implemented in the TSMC 90 nm CMOS process technology. As compared with the state-of-art master-and-slave MRF design, the experimental results show that not only the transistor count can be saved by 20%, the noise-tolerant performance can also be enhanced from 18.1 dB to 24.2 dB in the proposed common feedback MRF design.     

All-digital controlled boost DC–DC converter with all-digital DLL-based calibration

Traditional digital controls mostly use digital–analog converters to convert input and output voltages into digital coding to achieve control. This paper proposes the use of two digital ramps with two different frequencies to replace a digital–analog converter. This approach can produce seven bit resolution for the DPMW signal. In addition, we use an all-digital DLL phase correction concept to further enhance the resolution of the DPWM signal by an additional three bits, resulting in 10-bit DPWM signal resolution. The proposed circuit uses 0.35 μm CMOS processes, with a core area of 0.987 mm², a system switching frequency of 500 KHz, an input voltage range of 3.3–4.2 V, and an output voltage range of 5 V. Output voltage measurement accuracy reaches 99%, while the system reaches efficiency of 91% with output loads of up to 500 mA.     

五位RF MEMS开关延迟线移相器

设计并研制了一种6～11GHz、超宽带5位RF MEMS开关延迟线移相器,器件实现了5位延迟:λ、2λ、4λ、8λ、16λ。该器件采用微带混合介质多层板技术,分4层制作,尺寸为45mm×20 mm。整个器件包括20个RFMEMS悬臂梁开关,用60～75V的静电压驱动。6～11GHz频带内,对32个相移态的测试结果表明:一般回波损耗S11<-10dB,各状态平均插入损耗为-8～-10dB;中心频率处,器件可实现的最大延迟位时延为1680ps,总时延为3255ps。     

高精度大动态范围音频数字增益控制器设计

设计了一种用于音频领域的高精度大动态范围对数型数字增益控制器,实现了在音频范围内的电压到电压对数型衰减控制,衰减范围为0~-94.5 dB,单位衰减量为-1.5 dB。增益控制字为8位信号DIN[7∶0],内部使用18位R-2R结构DAC实现精确衰减控制,使用对数译码逻辑减少输入控制字位数。设计了具有低噪声特性的轨到轨运算放大器,等效输入噪声仅为10.7 nV/Hz@1 kHz。仿真结果表明,设计的对数型数字增益控制器具有工作电压低、动态范围大、衰减精度高、等效输入噪声低等优点。     

A 1.25 Gbps DC-coupled laser diode driver with VBE compensation technique

A 1.25 Gbps integrated laser diode driver (LDD) driving an edge-emitting laser has been designed and fabricated in 0.35 μm BiCMOS technology. The IC can provide independent bias current (5-100 mA) with automatic power control, and modulation current (4-85 mA) with temperature compensation adjustments to minimize the variation in extinction ratio. This paper proposed an unique modulation output driver configuration which is capable of DC-coupling a laser to the driver at +3.3 V supply voltage; and combined a V_BE compensation circuit, the IC can operate at a wide temperature range (−40 to 85 °C) for date rates up to 1.25 Gbps. V_BE compensation technique is used to compensate for variation in V_BE over the operating temperature range so as to minimize the variations in rise and fall time of modulation output over temperatures.     

High efficiency boost converter with variable output voltage using a self-reference comparator

This paper presents a boost converter with variable output voltage and a new maximum power point tracking (MPPT) scheme for biomedical applications. The variable output voltage feature facilitates its usage in a wide range of applications. This is achieved by means of a new low-power self-reference comparator. A new modified MPPT scheme is proposed which improves the efficiency by 10%. Also, to further increase the efficiency, a level converter circuit is used to lower the V_dd of the digital section. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. Using this approach, a thermoelectric energy harvesting circuit has been designed in a 180 nm CMOS technology. According to HSPICE Simulation results, the circuit operates from input voltages as low as 40 mV and generates output voltages ranging from 1 to 3 V. A maximum power of 138 μW can be obtained from the output of the boost converter which means that the maximum end-to-end efficiency is 52%.