Ensuring safety and efficiency in networks-on-chip

Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality of service requirements. In this work, we present a mechanism for a global and dynamic admission control in NoCs dedicated to real-time systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of system's utilization. Our mechanism does not require the modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.     

Design of a hard real-time multi-core testbed for energy measurement

This paper presents a systematic methodology for designing a hard real-time multi-core testbed to validate and benchmark various rate monotonic scheduling (RMS)-based task allocation and scheduling schemes in energy consumption. The hard real-time multi-core testbed comprises Intel Core Duo T2500 processor with dynamic voltage scaling (DVS) capability and runs the Linux Fedora 8 operating system supporting soft real-time scheduling. POSIX threads API and Linux FIFO scheduling policy are utilized to facilitate the design and Dhrystone-based tasks are generated to verify the design. A LabView-based DAQ system is designed to measure the energy consumption of CPU and system board of the testbed. A case study of task allocation and scheduling algorithms is also presented that aim to optimize the schedule feasibility and energy consumed by the processor and memory module in the multi-core platform. The experience from the implementation is summarized to serve as potential guidelines for other researchers and practitioners.     

Synthesizing Energy-Efficient Embedded Systems with LOPOCOS

In this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimization steps during design space exploration for DVS enable architectures. The optimization steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimization for scheduling and communication mapping based on genetic algorithm, optimizes simultaneously execution order and communication mapping towards the utilization of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimizationsteps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm.     

一种基于电压岛的片上网络低功耗设计

功耗问题一直是片上网络设计中最为关心的问题之一.基于全局异步局部同步(GALS)的电压岛(VFI)机制的引入不但提供了极大地降低片上功耗的可能,也解决了片上单时钟传输的瓶颈问题.本文改善了现有的两种电压岛划分、核映射及路由分配方法,提出了一种更优的综合解决方案,并进行了验证.仿真结果显示,本文的方案可以显著降低系统功耗,同时提高了片上网络性能.     

遗传算法在硬实时系统预调度中的应用

针对硬实时系统的特性,改进了遗传算法的初始群体生成方法及交换变异算子。实现了硬实时系统任务预调度。对给出的任务集合找出了最佳调度序列。通过测试集合仿真,效果良好。     

动态电压调整多处理器实时系统任务调度

动态电压调整DVS（Dynamic Voltage Scaling）是根据处理器电压（速度）降低之后，能量消耗平方级的减少这一原理提出的。文章通过DVS机制在多处理器实时系统中进行任务调度．通过对任务调度中的静态能量管理进行分析，在此基础上提出了一种新的基于DVS的适用于多处理器实时系统中的调度算法。这种新的调度算法是通过对贪婪法调度进行研究，发现其不足．并以此为基础进行改进。结合了动态电压调整的多处理器实时系统任务调度的能量消耗比普通的任务调度能量消耗有了很大的改善。     

Improving Memory Efficiency of Dynamic Memory Allocators for Real‐Time Embedded Systems

Dynamic memory allocators for real‐time embedded systems need to fulfill three fundamental requirements: bounded worst‐case execution time, fast average execution time, and minimal fragmentation. Since embedded systems generally run continuously during their whole lifetime, fragmentation is one of the most important factors in designing the memory allocator. This paper focuses on minimizing fragmentation while other requirements are still satisfied. To minimize fragmentation, a part of a memory region is segregated by the proposed budgeting method that exploits the memory profile of the given application. The budgeting method can be applied for any existing memory allocators. Experimental results show that the memory efficiency of allocators can be improved by up to 18.85% by using the budgeting method. Its worst‐case execution time is analyzed to be bounded.     

操作系统级低功耗动态电压缩放算法分析

低功耗的设计已经成为嵌入式系统设计中一个非常重要的方面，而动态电压调度（Dynamic Voltage Scaling DVS）又被认为是降低功耗的一种有效手段。本文对各类针对系统的动态电压缩放算法做了较系统的总结，给出了算法的模型，重点描述了操作系统级的两类动态电压缩放算法——基于间隔和基于任务的动态电压调度算法，概述了针对编译级的任务内动态电压调度算法。文章对三类算法作了分析与比较，由此给出了结论与观点，对以后动态电压缩放算法的研究做了预测。     

嵌入式系统动态电源管理预测算法研究

针对目前在嵌入式系统中动态电源管理普遍采用超时算法节能效率低的缺点,采用预测的方法进行动态电源管理.提出一个动态电源管理预测算法,该算法通过利用设备空闲状态的历史信息对未来的空闲时间进行预测,预测结果作为动态电源管理的依据.实验结果说明该算法对工作状态平稳的系统空闲预测效果比较理想,适用于动态电源管理.     

UbiFOS: A Small Real‐Time Operating System for Embedded Systems

The ubiquitous flexible operating system (UbiFOS) is a real‐time operating system designed for cost‐conscious, low‐power, small to medium‐sized embedded systems such as cellular phones, MP3 players, and wearable computers. It offers efficient real‐time operating system services like multi‐task scheduling, memory management, inter‐task communication and synchronization, and timers while keeping the kernel size to just a few to tens of kilobytes. For flexibility, UbiFOS uses various task scheduling policies such as cyclic time‐slice (round‐robin), priority‐based preemption with round‐robin, priority‐based preemptive, and bitmap. When there are less than 64 tasks, bitmap scheduling is the best policy. The scheduling overhead is under 9 µs on the ARM926EJ processor. UbiFOS also provides the flexibility for user to select from several inter‐task communication techniques according to their applications. We ported UbiFOS on the ARM9‐based DVD player (20 kB), the Calm16‐based MP3 player (under 7 kB), and the ATmega128‐based ubiquitous sensor node (under 6 kB). Also, we adopted the dynamic power management (DPM) scheme. Comparative experimental results show that UbiFOS could save energy up to 30% using DPM.     

战术空中侦察系统发展趋势

本文概要介绍了西方国家近代的战术空中侦察系统发展情况。从中可以比较清楚地看出技术发展的趋势及其规模，尤其是对于有效侦察系统所提出的系统性要求。     

应用于低功耗SoC的动态时钟管理技术

文章着重分析了基于系统级的低功耗技术,提出了动态时钟管理技术,介绍了其背景、原理以及在系统低功耗中发挥的重要作用。最后,将该技术应用到一款LCD控制器中。事实表明,动态时钟管理技术在保证系统性能的前提下,大大降低了功耗,取得了很好的效果。     

Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms

System-on-a-chip platform manufacturers are increasingly adding configurable features that provide power and performance flexibility, in order to increase a platform's applicability to a variety of embedded computing systems. We illustrate the energy benefits of combining the configurable features of voltage scaling and cache way shutdown in a single platform. We describe methods to assist a designer to tune such a platform to a particular software task and to particular energy optimization criteria.     

模块化多功能光纤检测系统

光纤测试大都使用多个独立设备组建测试环境,因其种类繁多,使测试过程中存在人为操作误差。为了解决此类问题,设计了将多个测试设备的功能合成一体的模块化多功能光纤检测系统,给出了该系统的硬件组成、软件组成以及实测数据。经过第三方检验机构的检验,结果表明该系统已达到目前台式测试设备指标,能够替换目前多个独立设备组建的测试环境。     

基于GMM的实时说话人识别系统

介绍了一个基于GMM实时说话人识别系统的设计与实现,系统具有实时说话人辨认和实时说话人确认功能。在实验室条件下,对不同的高斯混合密度个数及采样率进行了测试,测试了模型的自适应性能。实验表明系统具有较好的识别准确率。     

一种工控领域内存数据库的设计与实现

设计与实现了一种工控领域的内存数据库.给出了各模块的具体实现方法,重点给出了适合实时数据库特点的实时事务管理的方法和流程.在实际应用中,能够稳定而高效的运行.     

Synthesis of Hard Real-Time Application Specific Systems

This paper presents a system level approach for the synthesis of hard real-time multitask application specific systems. The algorithm takes into account task precedence constraints among multiple hard real-time tasks and targets a multiprocessor system consisting of a set of heterogeneous off-the-shelf processors. The optimization goal is to select a minimal cost multi-subset of processors while satisfying all the required timing and precedence constraints. There are three design phases: resource allocation, assignment, and scheduling. Since the resource allocation is a search for a minimal cost multi-subset of processors, we adopted an A* search based technique for the first synthesis phase. A variation of the force-directed optimization technique is used to assign a task to an allocated processor. The final scheduling of a hard-real time task is done by the task level scheduler which is based on Earliest Deadline First (EDF) scheduling policy. Our task level scheduler incorporates force-directed scheduling methodology to address the situations where EDF is not optimal. The experimental results on a variety of examples show that the approach is highly effective and efficient.     

Hard disk drive control by model based dual-rate controller. Computation saving by interlacing

This paper addresses the application of multirate control techniques to hard disk drives (HDD) single stage actuation. It applies a model-based dual-rate controller with computation saving at its implementation stage. The main goal is twofold: to study a new dual-rate control scheme in this kind of environment that, as it is known, provides the achievement of more storage space and to reach a saving in computation resources when using this specific dual-rate control. The dual-rate control is planed by considering an N times slower measurement -NT- but a faster frequency for control updating -T- being N a positive integer. The work introduces a new discrete lifting modelling step that allows to compute an exact frequency response that helps the controller implementation with computation saving by interlacing. A system output response improvement is obtained by using this methodology. A comparison with an usual single rate control including its implementation by interlacing is done based on a HDD laboratory set-up.     

多路图像实时采集侦察系统设计与实现

本文提出了一种基于VC++的实时图像解压显示处理系统,分析了系统的基本结构,对实时图像解压显示过程中涉及到的技术、算法及系统整体设计做了全面的论述。利用采集到的样本数据对该实时系统进行了分析和验证。系统的研制可以满足多路图像实时采集侦察系统的图像处理与传输的应用需求。     

用于开放式系统的二维优先级实时调度

提出了一种新的用于开放式系统的调度机制,即二维优先级实时调度,它不仅划分任务优先级,还划分调度策略优先级.任务的执行顺序由其调度策略优先级和任务优先级共同决定.它不仅可以解决传统优先级调度机制中机制与调度策略不能相分离的问题,还提高了效率.这种机制中引入的CPU带宽控制策略,可以根据需要实现硬实时、软实时、混合实时不同目标的实时系统,并简化了任务可调度性分析,且可以为不同权限或级别的用户提供不同QoS服务.这种调度架构不仅效率高,而且具有很强的开放性,适用广、易扩展.