Electromigration lifetime sudies of submicrometer-linewidth Al-Cu conductors

Electromigration in metal conductors used in VLSI circuits raises important concerns especially at submicrometer dimensions. In this paper, we show that the current-carrying capability required in submicrometer MOS technology can be quite severe. We show experimentally that the mean time to fail for Al-Cu conductors increases as the linewidth decreases below about 2 µm and well into the submicrometer regime. Concomitant with this increase in the mean time to fail, there is an increase in σ, the spread of the failure distribution as well, leading to decreased reliability at early times for very narrow lines. Grain size and geometry are used to explain our results. Our studies also show that the applicability of an unenhanced "lift-off" defined Al-Cu metallurgy for submicrometer NMOS application needs careful examination.     

Embossed-grating lead chalcogenide buried-waveguidedistributed-feedback lasers

The successful preparation and mode behavior analysis of buried double-heterostructure distributed-feedback (DFB) PbEuSe lasers using an embossing technique for the DFB submicrometer grating is reported here for the first time. The submicrometer grating was embossed with a silicon master grating. By our analysis of the mode spectra using a transfer matrix method, it was possible to distinguish precisely different positions of the laser facets due to the accidental cleaving relatively to the submicrometer grating     

Submicrometer- and nanometer-structure formation on the surface of epitaxial IV–VI semiconductor films by Ar-plasma treatment

A method is presented for fabricating submicrometer and nanometer structures on epitaxial films of a IV–VI compound semiconductor on a Si(111) substrate by sputtering with an RF-induction Ar plasma. The role is identified of threading dislocations and terraces on the film surface in the formation of submicrometer and nanometer hillocks. The relationship is determined of sputtering parameters to the RF bias and process time. The self-formation of submicrometer hillocks is traced to dislocation exit sites being masked by Al-containing components.     

Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

Degradation of device characterisitics due to hot-carrier injection in submicrometer PMOSFET has been investigated. We found that in submicrometer p-channel transistors the punchthrough voltage is seriously reduced due to hot-electon-induced punchthrough (HEIP). A worst case analysis of the experimental data shows substantially reduced lifetime due to HEIP.     

A gallium arsenide overlapping-gate charge-coupled device

We have developed a new CCD fabrication process for producing an overlapping gate structure which permits submicrometer control of the gap size while using conventional lithography. This process has been used to fabricate four-phase 16-stage Schottky barrier CCD's on GaAs with charge transfer inefficiencies of less than 2 × 10^-4at a 1-MHz clock rate, indicating that charge loss due to potential troughs between the gates has been essentially eliminated. This control of the gap permits the CCD channel to be of submicrometer thickness, which simplifies the integration of CCD's with high-speed devices requiring submicrometer channel thicknesses.     

A new edge-defined approach for submicrometer MOSFET fabrication

A novel technique employing vertical (anisotropic) dry etching for fabricating edge-defined submicrometer MOSFETs is described, and preliminary results are presented. Three basic process techniques are employed: formation of an edge-defined submicrometer element, pattern transfer of the element into an underlying doped polysilicon gate layer, and passivation of the FET using a sidewall oxide. The submicrometer element formation technique is limited to linewidths in the 0.1 µm to 0.4 µm range. Characterization of MOSFETs, having physical channel lengths ∼0.1 µm to 0.15 µm and believed to be the world's smallest MOSFET's reported to date, is discussed.     

An analytical drain current model for submicrometer and deepsubmicrometer MOSFET's

In this paper, we present a new, analytical, and physics-based drain current model for both submicrometer and deep submicrometer MOSFET's. The model was developed by starting from a two-dimensional (2D) Poisson equation and using the energy balance equation. Using the present model, we can clearly see that the drain current increases with decreasing channel length due to a larger average channel mobility at shorter channel length. The formulas for the saturation drain voltage and the drain current can be reduced to their corresponding well-known formulas in the submicrometer range. The accuracy of the presented model has been verified with the experimental data of metal-oxide-semiconductor (MOS) devices with various geometries     

Concentric Sub‐micrometer‐Sized Cables Composed of Ni Nanowires and Sub‐micrometer‐Sized Fullerene Tubes

Highly ordered arrays of submicrometer‐sized coaxial cables composed of submicrometer‐sized C₆₀ and C₇₀ tubes filled with Ni nanowires are successfully prepared by combining a sol–gel method with an electrodeposition process. The wall thickness of the submicrometer‐sized tubes can be adjusted by the concentration of fullerenes and the immersion time. The thermal stability of the submicrometer‐sized C₆₀ tubes is studied by Raman spectroscopy and it is found that these structures can be easily decomposed to form carbon nanotubes at relatively low temperatures (above 573 K) in an alumina template. These novel coaxial cable structures have been characterized by transmission electron microscopy (TEM), high‐resolution TEM (HRTEM), scanning electron microscopy (SEM), field‐emission SEM (FESEM), Raman spectroscopy, elemental mapping, energy dispersive X‐ray (EDX) spectroscopy, X‐ray diffraction (XRD), vibrating sample magnetometer (VSM) experiments, and superconducting quantum interference device (SQUID) measurements. Magnetic measurements show that these submicrometer‐sized cables exhibit enhanced ferromagnetic behavior as compared to bulk nickel. Moreover, submicrometer‐sized C₇₀/Ni cables show uniaxial magnetic anisotropy with the easy magnetic axis being parallel to the long axis of the Ni nanowires. C₇₀/Ni cables also exhibit a new magnetic transition at ca. 10 K in the magnetization–temperature (M–T) curve, which is not observed for the analogous C₆₀/Ni structures. The origin of this transition is not yet clear, but might be related to interactions between the Ni nanowires and C₇₀ molecules. There is no preferred magnetization axis in submicrometer‐sized C₆₀/Ni cables, which implies that the Ni nanocrystals have different packing modes in the two composites. These different crystalline packing modes lead to different magnetic anisotropy in the two composites, although the Ni nanocrystals have the same face‐centered cubic (fcc) structure in both cases.     

Oxidation rate reduction in the submicrometer LOCOS process

Experimental and analytical studies on submicrometer LOCOS oxide structures have been carried out. LOCOS oxide thickness reduction in submicrometer nitride windows has been newly observed. However, the bird's beak length remains constant, in spite of decreasing the nitride window to 0.3 µm. In order to explain these results, a simple oxidation model is experimentally introduced that considers the lateral diffusion of oxidants from the nitride edge. Oxide thickness reduction is due to the decrease of oxidants in the submicrometer nitride window. A locus for the isolation region length in the etched back LOCOS process is also given by using our model. The nitride window sensitivity for LOCOS oxide structures should be considered during the process design for miniature devices with a submicrometer feature size.     

Delay analysis of series-connected MOSFET circuits

In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V_DS and V_GS of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2-μm designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N². The delay dependence on input terminal position for SCMS structures is also described