VLSI金属互连线1/f γ噪声指数与电迁移失效

对VLSI的金属互连线实施高应力下的加速寿命试验和常规应力下的噪声频谱测量,得到了金属薄膜1/f ^γ噪声的频率指数γ在电迁移演化过程中的变化规律,发现γ指数在寿命试验的某个时间点发生突变,从1.0上升到1.6以上.这种突变可以归因于电迁移诱发空洞形成过程的起点,因而是金属薄膜结构开始发生不可逆结构变化的标志.1/ f ^γ噪声指数因子可望成为金属薄膜电迁移损伤程度或寿命的一个表征参量.     

VLSI金属互连电迁移可靠性评估技术研究

在简要介绍电迁移失效机理的基础上,对各种电迁移可靠性实验评估方法的特点进行了分析对比,重点研究了VLSI金属互连电迁移可靠性的噪声评估技术.通过实验数据和结果的对比分析,证明噪声方法不仅可行,而且有着其他传统方法不可比拟的优越性,具有极好的应用前景.     

用1/f~γ噪声检测VLSI金属薄膜互连的电迁移

金属薄膜互连的电迁移现象是VLSI最重要的可靠性问题之一。然而,常规的电迁移评价方法均需要较长的试验周期,而且具有一定的破坏性。近年来发展的1/f~γ噪声检测电迁移的方法以其快速、经济、非破坏性的特点,显示出诱人的应用前景。本文介绍了这一方法的研究现状与展望。     

VLSI的电迁移及其微测试技术

本文叙述了VLSI的性质,讨论了电迁移的微测试技术,包括噪声测试快速评估电迁移.标准晶片级电迁移加速试验,互连接触孔的电迁移检测以及应用标准测试结构控制金属膜的电迁移.     

基于低频噪声的薄膜电阻器可靠性表征方法

薄膜电阻的低频噪声同器件的损伤程度密切相关。文中采用两级低噪声放大器和高速高精度PCI数据采集卡构建的测试系统测量了一组1.5 kΩ镍铬薄膜电阻老化试验前后的低频噪声,结合显微分析发现电迁移是薄膜电阻可靠性退化的主导机制,电迁移损伤发生前后低频噪声的幅值、频率指数和转折频率等参量均会发生异常波动。分析表明,低频噪声能更敏感地反映薄膜电阻的损伤程度,可作为此类器件可靠性无损的筛选依据。     

镍铬薄膜电阻器噪声特性研究

薄膜电阻器的低频噪声有别于常规电阻器的噪声特征,与其结构和工艺密切相关。通过溅射工艺生产的阻值为1.5k?镍铬薄膜电阻器分别在生产完成和1000h老化试验之后进行了低频噪声测量和分析得到器件低频噪声特征,结合电子元器件低频噪声理论探讨了器件中各种噪声成分的来源及产生机制并给出该镍铬薄膜电阻生产线降低噪声的工艺手段。并讨论了电迁移损伤对1/f噪声特征的影响,指出噪声的异常波动对电迁移损伤具有明确的指示作用。     

集成电路可靠性电迁移评估技术

随着VLSI集成度的提高,金属化互连线的几何尺寸亦不断缩小,电迁移成为更为严重的可靠性问题,电迁移评估技术也越来越多.本文全面地总结了各种电迁移评估技术.     

SnAgCu凸点互连的电迁移

研究了无铅Sn96Ag3 sCuo s凸点与镀Ni焊盘互连界面的电迁移现象.在180℃条件下,凸点及互连界面在电迁移过程中出现了金属间化合物沿电子流运动方向的迁移,其演化过程呈现出显著的极性效应:阴极互连界面发生了金属间化合物的熟化、剥落和迁移;阳极互连界面则出现了金属间化合物的大量聚集.金属间化合物的演化和迁移造成了阴极处的物质减少,从而诱发空洞的形成和聚集,导致互连面积减小,整体电阻增大,可靠性降低.     

SnAgCu凸点互连的电迁移

研究了无铅Sn96Ag3 sCuo s凸点与镀Ni焊盘互连界面的电迁移现象.在180℃条件下,凸点及互连界面在电迁移过程中出现了金属间化合物沿电子流运动方向的迁移,其演化过程呈现出显著的极性效应:阴极互连界面发生了金属间化合物的熟化、剥落和迁移;阳极互连界面则出现了金属间化合物的大量聚集.金属间化合物的演化和迁移造成了阴极处的物质减少,从而诱发空洞的形成和聚集,导致互连面积减小,整体电阻增大,可靠性降低.     

集成电路互连线电迁移测试方法与评价

介绍了研究集成电路互连线电迁移的两种方法：加速寿命试验和移动速度试验。对加速寿命试验进行了分析和评价。分析表明,加速寿命试验方法存在高应力条件与正常工作条件下互连线电迁移中金属离子扩散机制不同、BLACK方程的使用范围有限、受试件特殊结构影响和电阻温度系数TCR随温度变化等问题。介绍了一种改进方法。详细介绍了移动速度试验,指出了其在互连线电迁移研究中的应用。     

Shape effect on electromigration in VLSI interconnects

The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely interconnections layout of VLSI circuits, reduce the lifetime of such interconnects. Substitutions by more gradual, smaller angled corners improve electromigration lifetimes.     

Combined low-frequency noise and resistance measurements for void extraction in deep-submicrometer interconnects

Electromigration stress can give rise to voids that increase the resistance and localized thermal stress in interconnects. Estimation of the extent of voiding can provide information on the material quality and the amount of degradation that has resulted from the electrical stress. In this paper, a model is proposed that can be used to estimate the effective void volume in deep-submicrometer interconnects. The model uses a combination of low-frequency noise and resistance measurements, and also considers the thermal coefficient of resistance in calculating the change in resistance of the interconnect line. A deconvolution scheme was employed to extract the 1/f noise component from the noise-measurements to improve the accuracy of the extraction algorithm. To verify the accuracy of the model, the focused ion beam (FIB) technique was used to mill holes (to simulate voids) of known dimensions. The model was further applied to an electromigration stress study of aluminum (Al) interconnects as a method of testing its validity for stress-induced voids. The proposed technique is a useful reliability tool for void detection in deep-submicrometer interconnects.     

Low-frequency noise measurement-based reliability testing of VLSI interconnects with different geometry

Low-frequency noise measurements were performed on thin metallic very large-scale integration (VLSI) interconnects of three different geometries. These measurements were carried out under stressing current densities between 1.0/spl times/10/sup 5/ A/cm/sup 2/ and 2.2/spl times/10/sup 6/ A/cm/sup 2/ at different ambient temperatures up to 280/spl deg/C, in order to investigate the dependence of low-frequency noise on the geometrical shape of the VLSI interconnects. The behavior of these samples under these conditions is analyzed in this letter.     

A fast wafer-level screening test for VLSI metallization

A method for screening out poor-quality metallizations from VLSI fabrication lines by wafer-level probing is proposed. Theoretical analysis suggests a linear dependence of the metal line conductance on the square of the current density, at thermal equilibrium. The limit to this linearity for ideally perfect metallizations occurs at the metal melting point, at which there is a sudden decrease in the conductance value to zero. In real interconnects, nonidealities such as localized defects or nonuniform surrounding dielectric at isolated points could lead to a deviation of the conductance from ideal expectations. Using this as a diagnostic, a universal methodology for assessing metal quality, independently of the physical parameters of the metal line, is described. Qualitative correlation with electromigration lifetime results is used to validate the method     

Reliability of metal interconnect after a high-current pulse

In certain situations, very large scale integration (VLSI) metal interconnects are subjected to short duration high current pulses. This occurs in FPGA programming, and in radiation testing for latchup. The authors have determined the effects of such pulsing on the long term reliability of Al (1% Cu) metallization with W cladding on top and bottom. The reliabilities of pulsed and unpulsed lines were established using accelerated electromigration testing. Lines pulsed below the immediate catastrophic threshold were seen to have slightly improved electromigration lifetimes, but as the failure threshold is approached, electromigration lifetime decreases abruptly. Therefore, high current pulsing provides no reliability hazard in this metallization system below catastrophic threshold     

Noise and reliability in simulated thin metal films

Many macroscopic aspects of electromigration damage in thin metal films have been investigated by means of Monte Carlo simulations based on simplified physical model. The employed model, can be described as a middle-scale model, in which the physical system is modeled with a high level of abstraction, without a detailed atomic physical model of the system.Among the many effects of the electromigration phenomenon, the simulator has been used to investigate several statistical properties of electromigration failure and the noise behaviour.Notwithstanding this simplicity, it is able to generate results in good agreement with many experimental observations: the lognormal distribution of failures, dependence of the mean time to failure from stress current and film geometry, Black exponent, noise statistics.Furthermore, this simulations confirmed a significant correlation between electromigration noise in the initial phase of stress and time to failure which has been suggested by a few experimentalists. This correlation can be usefully exploited as an early indication of the onset of electromigration damage on a per-sample basis.     

The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

With the continuous advancement of semiconductor technology,the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date,most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all,an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly,the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level,intermediate level and global level,respectively.Moreover,the experimental results show that the CMS interconnects have lesser noise peak,noise width and noise amplitude than the VMS interconnects in the same cases,and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system.     

考虑工艺波动的互连串扰的峰值统计模型

随着集成电路特征尺寸的不断减小,互连线的串扰噪声对工艺波动的灵敏度也在相应增加。通过分析互连几何参数波动对互连寄生参数的影响,得到其近似的函数关系表达式,在此基础上建立了考虑工艺波动的串扰噪声的统计模型。利用该模型可以得到互连串扰噪声均值和标准差的解析表达式。计算结果表明：和HSPICE相比,该方法在确保计算精度的前提下大大缩短了计算时间,在超大规模集成电路互连信号完整性的分析和优化中具有一定的应用前景。     

Crosstalk modeling for coupled RLC interconnects with application to shield insertion

On-chip interconnect delay and crosstalk noise have become significant bottlenecks in the performance and signal integrity of deep submicrometer VLSI circuits. A crosstalk noise model for both identical and nonidentical coupled resistance-inductance-capacitance (RLC) interconnects is developed based on a decoupling technique exhibiting an average error of 6.8% as compared to SPICE. The crosstalk noise model, together with a proposed concept of effective mutual inductance, is applied to evaluate the effectiveness of the shielding technique.