适用于中国超宽带标准的0.18μm-CMOS单边带混频器设计

基于0.18 μm-CMOS工艺设计了一款适用于中国超宽带(UWB)标准的单边带(SSB)混频器.对电流换向型混频器进行分析,提出折叠PMOS跨导级结构使线性度和转换增益得以同时提升,并应用并联峰化技术扩展电路带宽,满足了系统超宽带、高线性度和增益适中的要求.结果表明,在6 GHz～9 GHz范围内,转换增益大于-2 dB且增益平坦,镜像抑制约为90dB,IP-1dB大于0 dBm,ⅡP3大于10 dBm.电路核心面积0.35mm×0.65 mm,工作电压为1.8 V,直流电流10.6 mA.     

适用于中国超宽带标准的0.18um-CMOS单边带混频器设计

基于0.18um-CMOS工艺设计了一款适用于中国超宽带（UWB）标准的单边带（SSB）混频器。本文对电流换向型混频器进行分析,提出折叠PMOS跨导级结构使线性度和转换增益得以同时提升,并应用并联峰化技术扩展电路带宽,满足了系统超宽带、高线性度和增益适中的要求。结果表明,在6GHz～9GHz范围内,转换增益大于-2dB且增益平坦,镜像抑制约为90dB,摄入1dB压缩点大于0dBm,IIP3大于10dBm。电路核心面积0.35mm×0.65mm,工作电压为1.8V,直流电流10.6 mA。     

30～2 600 MHz超宽带GaN功率放大器的设计与实现

基于第三代半导体GaN的高电子迁移率晶体管技术,利用Cree CGH40010管芯大信号模型并结合ADS2009U1软件,结合商用GaN管芯的自身特性,采用微带-电阻-微带-电容-微带的负反馈回路和整体负载牵引方法及宽带匹配网络,成功设计并实现了30～2 600 MHz超过6个倍频程的超宽带功率放大器.测试结果表明,该功率放大器的带内线性增益大于11.8 dB,线性增益平坦度小于±0.95 dB,输入回波小于-10.2 dB,1 dB压缩点输出功率大于36.5 dBm,功率附加效率大于22％,饱和时输出功率大于39.1 dBm,功率附加效率大于28％.该功率放大器在很宽的频带内有着平坦的增益,适用于对平坦度要求较高的超宽带系统中.     

单片高线性度低噪声宽带解调器设计

设计了一款单片高线性度低噪声宽带解调器.采用共基极输入吉尔伯特单元混频器结构实现宽带和高线性度特性,内部集成螺旋线圈变压器,实现单端向双端转换.电路采用0.18μmSiGe BiCMOS工艺技术,在2～4 GHz频段内实现宽带匹配,反射系数小于-10dB,单边带噪声系数小于14dB,输入1dB压缩点大于10dBm,相位误差小于1.5°,幅度误差小于0.5 dB.     

Ka波段5W GaAs PHMET功率MMIC

报道了一款采用0.15μm GaAs功率MMIC工艺研制的Ka波段功率放大器芯片。芯片采用四级放大拓扑结构,在29～32GHz频带范围内6V工作条件下线性增益25dB,线性增益平坦度小于±0.75dB;饱和输出功率大于5W,饱和效率大于20%,功率增益大于22dB;1dB压缩点输出功率大于36.5dBm,效率大于18%。     

基于氮化铝技术的表贴型微波封装

采用氮化铝多层布线技术,运用垂直过渡方式实现微波信号从基板底部到表面的信号传输,完成表贴式微波封装设计。在DC-18GHz内,该表贴互连反射损耗小于-15dB,插入损耗小于1.0dB。采用该技术封装了6～18GHz宽带放大器,封装尺寸为5mm×5mm×1.2mm,频带内反射损耗小于-10dB,增益15dB,平坦度小于1dB;另外还封装C波段5W功率放大器,封装尺寸为8mm×8mm×1.2mm,带内增益大于25dB,反射损耗小于-10dB,饱和输出功率37dBm,效率35%。采用技术的表面贴装放大器性能上能够满足微波通信、雷达应用,可用回流焊安装,适合规模生产。     

面向太赫兹辐射计应用的宽带接收机芯片

设计一款工作在W波段的辐射计SOC芯片。该芯片采用商用0.1μm栅长的GaAs pHEMT工艺;内部集成低噪声放大器,IQ输出的零中频电阻混频器以及6倍频本振链。测试结果显示,该芯片工作频率为85～110 GHz,中频带宽大于10 GHz,本振需求低于16 GHz&6 dBm;工作频带内整个接收机电路的变频增益大于7 dB,特别在98～105 GHz频带内平坦度优于±0.5 dB。此外,该芯片实现了优于35 dBc的镜频抑制,极大降低了接收电路前级滤波器的需求。     

采用ADS的CMOS双平衡混频器设计

分析了Gilbert结构有源双平衡混频器的工作机理,以及混频器的转换增益、线性度与跨导、CMOS沟道尺寸等相关电路参数间的关系,并据此使用ADS软件进行设计及优化。在采用TSMC 0.25μm CMOS工艺,射频信号为2.5GHz,本振信号为2.25GHz、中频信号为250MHz时,2.5V工作电压的情况下仿真得到的转换增益为10.975dB,单边带噪声系数为9.09dB,1dB压缩点为1.2dBm,输出三阶交调截止点为11.354dBm,功耗为20mW。     

一种新的射频CMOS混频器结构

提出了一种低电压高增益CMOS下变频混频器的新结构.这个结构避免了堆叠晶体管,因此可以在低电压下工作.在LO信号的频率为1.452GHz,RF信号频率为1.45GHz的情况下,仿真结果表明:混频器的增益为15dB,ⅡP3为-4.5dBm,NF为17dB,最大瞬态功耗为9.3mW,直流功耗为9.2mW.并对该混频器的噪声特性和线性度进行了分析.     

一种高线性无源双平衡混频器

设计了一种适用于1.0～2.0 GHz的高线性下变频混频器。电路设计采用了无源双平衡结构,片内集成宽带巴伦、限幅本振放大器、混频核和偏置电路。为了提高混频器的线性度,在对无源双平衡的结构进行分析的基础上,折中选择混频核的晶体管尺寸,并优化了本振放大器输出信号的幅值及上升时间。基于0.35μm BiCMOS工艺进行了设计仿真,芯片面积为0.9 mm×1.8 mm。流片测试结果表明:射频频率1.0～2.0 GHz,对应本振频率1.0～2.0 GHz,最佳本振输入功率为0 dBm,转换增益大于-7.0 dB,射频输入三阶交调大于25 dBm,混频器工作电压为3.3 V,功耗为112 mW。该高线性无源双平衡混频器可满足工程应用。     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

Design of a low noise distributed amplifier with adjustable gain control in 0.15μm GaAs PHEMT

正A low noise distributed amplifier consisting of 9 gain cells is presented.The chip is fabricated with 0.15-μm GaAs pseudomorphic high electron mobility transistor(PHEMT) technology from Win Semiconductor of Taiwan.A special optional gate bias technique is introduced to allow an adjustable gain control range of 10 dB.A novel cascode structure is adopted to extend the output voltage and bandwidth.The measurement results show that the amplifier gives an average gain of 15 dB with a gain flatness of±1 dB in the 2-20 GHz band.The noise figure is between 2 and 4.1 dB during the band from 2 to 20 GHz.The amplifier also provides 13.8 dBm of output power at a 1 dB gain compression point and 10.5 dBm of input third order intercept point(IIP3),which demonstrates the excellent performance of linearity.The power consumption is 300 mW with a supply of 5 V,and the chip area is 2.36×1.01 mm~2.     

应用于C-X-Ku波段的宽带功率放大器

采用0.25μm AlGaAs/InGaAs/GaAs PHEMT工艺技术,研制出了6～18GHz三级MMIC全匹配宽带功率放大器单片.在6～18GHz的工作频率下,放大器的平均功率增益为19dB,输出功率大于33.3dBm,在10GHz处有最大输出功率34.7dBm,输入回波损耗S11低于-10dB,输出回波损耗S22低于-6dB.与报道的C-X-Ku频段宽带功率放大器相比,有较好的功率平坦度.     

一种输出匹配可调的、高线性度宽带功率放大器

采用自适应偏置技术和有源电感实现了一款输出匹配可调的、高线性度宽带功率放大器(PA)。自适应偏置技术抑制了功放管直流工作点的漂移,提高了PA的线性度。有源电感参与输出匹配,实现了输出匹配可调谐,该策略可调整因工艺偏差、封装寄生造成的输出匹配退化。利用软件ADS对电路进行验证,结果表明,在4 GHz频率下,输入1dB压缩点(Pin 1dB)为-7dBm,输出1dB压缩点(Pout 1dB)为11dBm,功率附加效率(PAE)为8.7%。在3.1GHz~4.8 GHz频段内,增益为(20.3±1.1)d B,输入、输出的回波损耗均小于-10dB。     

A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process

This paper presents the design and integration of a fully-integrated dual-conversion zero-IF2 CMOS transceiver for 9-band MB-OFDM UWB systems from 3.1 GHz to 8.0 GHz. The transceiver integrates all building blocks including a variable-gain wideband LNA, a single combined mixer for both RF down-conversion in RX and up-conversion in TX, a fast-settling frequency synthesizer, and IQ ADCs and DACs. Fabricated in a standard 0.18- mum CMOS process, the receiver measures maximum S11 of - 13 dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatches of the receiver chain are measured to be 0.8 dB and 4 ^deg, respectively. The transmitter achieves a minimum output P-1 dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than - 46.5 dBc.     

E波段倍频放大模块设计

E波段是毫米波中非常重要的频段,也是较为缺乏研究的频段。E波段可三倍频至亚毫米波频段,其中220 GHz是大气吸收窗口,具有非常重要的研究价值。基于此,文中设计了一款E波段倍频放大模块,为220 GHz太赫兹发射机提供三倍频源信号,该模块输入频率为11.1~13.34 GHz,输出频率为66.6~80 GHz,输入功率为4~5 dBm,输出功率>18 dBm,增益>13 dB,具有较好的输出功率平坦度。该模块的成功研制为亚毫米波收发模块提供了功率源条件。     

A broadband highly linear BiCMOS mixer for direct conversion applications

A highly linear BiCMOS double balanced mixer for direct conversion applications is described and optimized. Based on the combination of active and resistive concepts, and modeled as a variable feedback amplifier, it achieves a high linearity and a good conversion gain. The performances achieved are; a conversion gain up to 12 dB, an output P/sub -1 dB/ of -5 dBm, and a high linearity, with an OIP3 of about +23 dBm and an OIP2 not less than +54 dBm, while requiring a local oscillator power no more than +4 dBm. As it covers a broadband RF spectrum, it can be used for receiving all communication networks located from 0.9 GHz until 2.2 GHz. When active, it drains 6 mA from 3.6 V.     

A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18-$mu$ m SiGe BiCMOS Technology

This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P_-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm².     

A 5.7–6.4GHz GaAs HBT Power Amplifier with a Gain Enhanced Bias Circuit

This paper describes the design of a 5.7–6.4GHz GaAs Heterojunction bipolar transistor (HBT) power amplifier for broadband wireless application such as wireless metropolitan area networks. A bias circuit is proposed which enhances the power gain and provides a good linearity. Using the wideband matching network tech-niques with trap circuits embedded to filter the harmonics and the diode-based linearizing techniques, a broadband power amplifier module was obtained which exhibited a gain above 28dB. This is about 1dB improvement com-pared with those normal bias circuits at a supply volt-age of 5V in the frequency range of 5.7–6.4GHz, measured with Continuous wave(CW) signals. The saturated output power was greater than 33dBm in 5.7–6.4GHz and the out-put 1dB compression point was greater than 31dBm. The phase deviation was less than 5 degrees when the output power below 33dBm. The second and third order harmonic components were also less than -45dBc and -50dBc.