A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time constant between the two input signal paths. All these skills are verified by simulation in the design of the 1.8-V 11-bit 40-MHz ADC in a 0.18-μm CMOS process with power dissipation 21-mW, signal-to-noise-and-distortion ratio (SNDR) 65-dB, effective number of bit (ENOB) 10.5-bit, spurious free dynamic range (SFDR) 78-dB, total harmonic distortion (THD) −75.4-dB, signal-to-noise ratio (SNR) 65.4-dB and figure-of-merit (FOM) 0.18 pJ/step.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

A dual-band direct-conversion RF front-end for WiMedia UWB receiver

This paper describes a direct-conversion RF front-end designed for a dual-band WiMedia UWB receiver. The front-end operates in band group BG1 and BG3 frequencies. It includes multi-stage LNAs, down-conversion mixers, a polyphase filter for quadrature local oscillator (LO) signal generation, and LO buffers. The UWB receiver is targeted for a mobile handset, where several other radios can be simultaneously on. Therefore, special attention was paid on minimizing the interference from different wireless systems. The front-end achieves approximately 26-dB gain and 4.9–5.6-dB noise figure (NF) across three sub-bands of BG1. In BG3 mode it obtains 23–26-dB gain and 6.9–7.7-dB NF. The front-end consumes 48.1 and 42.7 mA from a 1.2-V supply voltage in BG1 and BG3 operation modes, respectively. The chip was implemented in a 0.13-μm CMOS.     

A 1.5-V 2–9.6-GHz Inductorless Low-Noise Amplifier in 0.13-μm CMOS

This paper presents an inductorless low-noise amplifier (LNA) design for an ultra-wideband (UWB) receiver front-end. A current-reuse gain-enhanced noise canceling architecture is proposed, and the properties and limitations of the gain-enhancement stage are discussed. Capacitive peaking is employed to improve the gain flatness and -3-dB bandwidth, at the cost of absolute gain value. The LNA circuit is fabricated in a 0.13-mum triple-well CMOS technology. Measurement result shows that a small-signal gain of 11 dB and a -3-dB bandwidth of 2-9.6 GHz are obtained. Over the -3-dB bandwidth, the input return loss is less than -8.3 dB, and the noise figure is 3.6-4.8 dB. The LNA consumes 19 mW from a low supply voltage of 1.5 V. It is shown that the LNA designed without on-chip inductors achieves comparable performances with inductor-based designs. The silicon area is reduced significantly in the inductorless design, the LNA core occupies only 0.05 mm², which is among the smallest reported designs.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems

A 0.13-mu m CMOS fourth-order notch filter for the rejection of the 5-6 GHz interference in UWB front-ends is reported. The filter is integrated into an analog front-end for Mode #1 UWB. A thorough analysis based on a simplified model of the filter is carried out. An algorithm for the automatic tuning and calibration of the filter is also discussed and demonstrated. Two versions of the circuit are designed and fabricated: the first comprises a low-noise amplifier and the filter, and the second expands it to a complete front-end. In the latter version the filter was also redesigned. The filter provides more than 35 dB of attenuation and has a tuning range of 900 MHz, adding less than 30% power consumption to the LNA. The out-of-band IIP3 (higher than -13.2 dBm with the filter off) takes a 9-dB advantage from the filter and the compression of the gain due to the out-of-band blocker is reduced by at least 6 dB in the complete front-end. The conversion gain of the front-end is 25 dB per channel, its average noise figure is lower than 6.2 dB, and its in-band 1-dB compression point is higher than - 30 dBm at a power consumption of 32 mW.     

A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers

A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.     

Fiber-optic multigigabit GaAs MIC front-end circuit with inductorpeaking

The design and performance of a multigigabit optical front-end circuit are discussed. Inductor peaking is applied to the GaAs MIC preamplifiers and a 3-dB down bandwidth of 6.5 GHz, 15.5-pA/√Hz averaged input equivalent noise current density from 10 MHz to 6.5 GHz, and transimpedance gain of 57 dB are achieved. A 3-dB down bandwidth of 6.1 GHz is achieved in an optical front-end circuit with a InGaAs p-i-n photodiode. This performance indicates that the optical front-end circuit with inductor peaking is promising for multigigabit optical receivers     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

A silicon bipolar transmitter front-end for 802.11a and HIPERLAN2 wireless LANs

A 5-GHz transmitter front-end for 802.11a and HIPERLAN2 wireless local area networks was implemented in a low-cost 46-GHz-f/sub T/ silicon bipolar technology. The transmitter includes a digitally controlled linear-in-dB variable-gain up-converter and a three-stage linear power amplifier. At a 3-V supply voltage, the front-end exhibits a 23.5-dBm output 1-dB compression point, 35-dB maximum power gain, and 30-dB dynamic range. The dB-linear gain error is lower than /spl plusmn/0.8 dB. The transmitter is able to comply with the stringent error vector magnitude requirement of the standard up to a 19-dBm output power level.     

A 24-GHz Patch Array with a Power Amplifier/Low-Noise Amplifier MMIC

This paper presents an active patch array designed at 24 GHz. It can be used as a front-end component for a phased array. A series resonant array structure is chosen which is compact and easy excite. With 5 elements, the array proved a 12-dB antenna gain. A power amplifier and a low noise amplifier are designed on a single GaAs chip (PALNA). Bias switch is used in the PALNA, which greatly reduces the switch loss in a transceiver and increases the efficiency. 20-dB small signal gain is achieved in both power amplifier and low noise amplifier. The active patch array is built by the combination of the patch array and PALNA. The measured active gain of this antenna is 35-dB for the PA mode and 31-dB for the LNA mode. This active patch array can obtain an EIRP of 34 dBm with a total radiated power of 22dBm and a maximum PAE of 32%. To check the noise performance, we applied sources at both normal temperature and 77K (liquid nitrogen) and extracted the noise figure (3.5 dB) of the active antenna by the Y factor method. The results proved that the active antenna is working efficiently as both a transmitting and receiving antenna.     

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively     

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibitdelta-sigma modulation at 8× oversampling ratio

A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8× oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm² chip in 0.5-μm CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

A 0.18-$muhbox m$CMOS Selective Receiver Front-End for UWB Applications

This paper addresses the problem of 5–6-GHz WLAN interferer rejection in a direct-conversion receiver front-end for multi-band orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) applications. The IC, realized in a 0.18-$muhbox m$CMOS technology, comprises a single-ended voltage–voltage feedback low-noise amplifier (LNA) and a quadrature mixer. The LNA employs a double-peak single-notch network in the output load, amplifying UWB groups #1 and #3, while rejecting WLAN interferes in the 5–6-GHz frequency range. The mixer, based on a merged quadrature topology, also realizes a second-order low-pass filtering. Fabricated dies have been bonded on PCB for characterization. The front-end, drawing 10 mA from 1.8 V, achieves a 1-dB gain desensitization with a$-$6.5-dBm interferer power at 5.5 GHz. Other measured performances are 5.2-dB and 7.7-dB minimum and maximum noise figure (NF),$-$3.5-dBm minimum IIP3 and$+$34.5-dBm minimum in-band IIP2 and$+$21-dBm out-of-band IIP2.     

Integrated polarization diversity front end optics

The integration of a polarization-diversity receiver front-end suitable for balanced detection has been realized by the hybrid combination of a 3-dB directional coupler and a thin-film polarization beam splitter (PBS) fabricated on silica-based waveguides. Insertion losses, excluding the intrinsic loss of the coupler, were 1 and 1.2 dB for TE- and TM-polarizations, respectively. The polarization cross talk was less than -23 dB     

Broad-band GaAs monolithic equalizing amplifiers formultigigabit-per-second optical receivers

The authors discuss the development of ICs (integrated circuits) for a preamplifier, a gain-controllable amplifier, and main amplifiers with and without a three-way divider for multigigabit-per-second optical receivers using a single-ended parallel feedback circuit, two (inductor and capacitor) peaking techniques, and advanced GaAs process technology. An optical front-end circuit consisting of a GaAs preamplifier and an InGaAs p-i-n photodiode achieves a 3-dB bandwidth of 7 GHz and -12-dBm sensitivity at 10 Gb/s. Moreover, a gain-controllable amplifier obtains a maximum gain of 15 dB, a gain dynamic range of 25 dB, and a 3-dB bandwidth of 6.1 GHz by controlling the source bias of the common-source circuit. Gain, 3-dB bandwidth, and output power of the main amplifier with the three-way divider are 17.4 dB, 5.2 GHz, and 5 dBm, respectively. These ICs can be applied to optical receivers transmitting NRZ signals in excess of 7 Gb/s     

A GaAs double-balanced dual-gate FET mixer IC for UHF receiver front-end applications

A double-balanced dual-gate FET mixer has been developed for application in the front-end circuit of UHF receivers. A 6-8-dB conversion gain has been obtained without an additional matching circuit over a wide frequency range from 100-800 MHz with good suppression of RF/LO feedthrough by more than 20 dB and third-order intermodulatian product of -60 dB.     

A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.