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1.
TN7022007061054基于VHDL语言的有限域正则基乘法器设计/李月乔(华北电力大学电气与电子工程学院)//电讯技术.―2006,46(6).―63~66.有限域的运算已经广泛应用于Reed-Solomon码、存储领域和各种加密算法中。乘法运算是其中最复杂的一种运算,有限域中的元素可以用各种基表示。文中在给出有限域元素自然基下的表示方法的基础上,推导出了域元素正则基下的表示方法,并给出了正则基下域元素的乘法运算,编写了乘法器的VHDL模型。用XILINX公司的ISE5.2软件对电路模型进行了仿真,结果表明乘法器的运算结果完全正确。图1表2参5TN702200706…  相似文献   

2.
本文研究采用对偶基表示域元域时Reed-Solomon码的编码和译码问题。首先介绍一般基和对偶基表示下域元素之间的转换关系,而后讨论两种表示下域元素的乘法运算。特别细致分析了普通(?)对偶(?)对偶的串行乘法器的原理和实现框图。最后详细讨论了以这种乘法器简化实现Reed-Solomon码的编、译码器的原理和框图。  相似文献   

3.
椭圆曲线密码系统高速实现的关键是点的数乘与加法,实现点的数乘与加法要在基域中做大量的算术运算,其中最耗时的是域元素的乘法。本文给出了一类有限域GF(2m)中乘法的快速实现方法,该方法简单、高效,容易硬件实现。  相似文献   

4.
方冰  樊海宁等 《电子学报》2002,30(12A):2045-2048
有限域GF(2^n)上的椭圆曲线密码体制以其密钥短,安全强度高的优点正在获得广泛的重视和应用。该密码体制最主要的运算是有限域上的乘法运算。本文提出了一种基于Ⅱ型优化正规基的乘法器,该乘法器具有Massey-Omura乘法器的优点,又避免了其不足,易于编程,适合FPGA实现,实验表明,该算法简单,快速。  相似文献   

5.
GF(2n)域上的一种Ⅱ型优化正规基乘法器及其FPGA实现   总被引:1,自引:0,他引:1       下载免费PDF全文
方冰  樊海宁  戴一奇 《电子学报》2002,30(Z1):2045-2048
有限域GF(2n)上的椭圆曲线密码体制以其密钥短,安全强度高的优点正在获得广泛的重视和应用.该密码体制最主要的运算是有限域上的乘法运算.本文提出了一种基于Ⅱ型优化正规基的乘法器,该乘法器具有Massey-Omura乘法器的优点,又避免了其不足,易于编程,适合FPGA实现.实验表明,该算法简单,快速.  相似文献   

6.
首先介绍了有限域GF(2m)元素不同的基的表示,在此基础上讨论了有限域中常系数乘法器、串行乘法器及并行乘法器的硬件实现。重点介绍了适合高速RS编译码器实现的对偶基比特并行乘法器,并分析了比特并行对偶基乘法器的硬件时延、占用资源的大小。最后对不同乘法器进行了比较。与"查表法"及正规基并行乘法器相比,对偶基比特并行乘法器在速率和硬件规模上有较大优越性。  相似文献   

7.
F2^n上基于ONB的椭圆曲线乘法器的设计与实现   总被引:1,自引:0,他引:1  
文章在介绍有限域运算法则,域上椭圆曲线及点的运算法则的基础上,设计了一个F2^n上基于优化正规基的串行椭圆曲线乘法器,其点乘运算速度可达80.87次/秒,为进一步完成椭圆曲线加密系统提供了硬件基础。  相似文献   

8.
本文提出了有限域上的一个新性质:用变元为域元素的多项式表示域元素的分量.基于等价类的划分、线性方程组的求解和标准基之对偶基的计算,提出了域元素分量代数表达式的三种求法.以此解释了Rijndael算法S盒代数表达式复杂度低的本质原因,给出其分量函数间等价关系的一种直接证明方法.  相似文献   

9.
介绍一种新型有限域乘法器,其基本原理是引入多项式拆分概念和多项式拆分方法,将m次的多项式拆分成两个m/2次多项式分别做有限域乘法,这样可以降低乘法运算的阶数,用加法计算电路来代替。并且根据这种算法设计了新型乘法器的电路实现,将这种新型乘法器并且与比特串行乘法器的仿真结果做对比。结果表明新型的有限域乘法器达到了较高的系统数据吞吐率,可以应用于纠错系统、RS编码器和译码器中。  相似文献   

10.
文章在介绍有限域运算法则,域上椭圆曲线及点的运算法则的基础上,设计了一个F1291上基于优化正规基的串行椭圆曲线乘法器,其点乘运算速度可达80.87次/秒,为进一步完成椭圆曲线加密系统提供了硬件基础。  相似文献   

11.
Galois fields GF(2m) are used in modern communication systems such as computer networks, satellite links, or compact disks, and they play an important role in a wide number of technical applications. They use arithmetic operations in the Galois field, where the multiplication is the most important and one of the most complex operations. Efficient multiplier architectures are therefore specially important. In this paper, a new method for multiplication in the canonical and normal basis over GF(2m) generated by an AOP (all-one-polynomial), which we have named the transpositional method, is presented. This new approach is based on the grouping and sharing of subexpressions. The theoretical space and time complexities of the bit-parallel canonical and normal basis multipliers constructed using our approach are equal to the smallest ones found in the literature for similar methods, but the practical implementation over reconfigurable hardware using our method reduces the area requirements of the multipliers. José Luis Ima?a is Assistant Professor of Computer Architecture in the Department of Computer Architecture, Complutense University of Madrid (Spain). He received the Ph.D. degree in Physics from the Complutense University in 2003. His current research interests are computer architectures, VLSI technologies, logic design and verification, finite field arithmetic and cryptography. Juan M. Sánchez-Pérez is Professor of Computer Architecture in the Department of Computer Science, University of Extremadura, Spain. He received a PhD degree in Physics from the University Complutense of Madrid in 1976. His research interests are modern computer architectures, VLSI technologies and logic design.  相似文献   

12.
This paper presents a very large-scale integration implementation of Galois field arithmetic for high-speed error-control coding applications that is based on the field GF(p/sup m/) with m a small integer such as 2 or 3 and p a prime of sufficient value to generate the required field size. In this case, the Galois field arithmetic operations of addition, multiplication, and inversion are based on architectures using blocks that perform integer arithmetic modulo p. These integer arithmetic operations modulo p have previously been implemented with low delay power products through the use of one hot coding and barrel shifters circuits based on transistor arrays. In this paper, the same one hot coding and barrel shifters circuits are used to construct circuits that implement addition, multiplication, and inversion over GF(p/sup m/). The circuits for GF(p/sup m/) addition and multiplication with p/spl ne/2, achieve a lower power-delay product than designs based on GF(2/sup m/). Also, the architecture for GF(p/sup m/) inversion can be efficiently implemented when m=2 or m=3.  相似文献   

13.
A new model for metal-insulator-metal shunt capacitors is introduced in this paper. The main difference between the new model and known models is that critical parts of the capacitor's geometry are represented by black boxes. These boxes contain S-parameter files generated with an electromagnetic field solver. The capacitor parts, which depend on the capacitance value, are represented by microstrip and lumped elements. The new model combines the advantages of field simulations with those of lumped- or microstrip-based models. It can easily be used in circuit simulators utilizing their features for design development such as optimizations. The model is compared with two shunt capacitors on microwave monolithic integrated circuits to show the excellent fit  相似文献   

14.
在支持预搜索的面积紧凑型BCH并行译码电路中,采用双路选通实现结构,在校正子运算电路的输入端完成被纠码序列与有限域常量的乘法,简化了电路结构;在实现IBM迭代算法时,为了压缩实现面积,复用一个有限域GF(2n)上的二输入乘法器,一轮迭代运行多拍运算:设计了全组合逻辑预搜索模块,加快了BCH截短码的搜索速度.同现有技术相比,该译码电路实现面积紧凑且关键路径短.综合与静态时序分析结果表明,对于512字节的信息元和8-bit的纠错能力,该译码器在80MHz工作频率下符合时序要求;在TSMC 0.18μm工艺库下仅需约14800门,满足目前大容量存储设备对数据可靠性和成本控制的要求.  相似文献   

15.
李月乔  杜曼 《电讯技术》2004,44(5):148-152
基于有限域上多项式乘法理论,采用高层次设计方法,采用CPLD实现了GF(2^8)上8位快速乘法器,利用XILINX公司的Foundation Series3.1i集成设计环境完成了快速乘法器的VHDL源代码输入、功能仿真、布局与布线、时序仿真,并用XC9572PC84可编程逻辑芯片验证了该电路设计。该乘法器可以应用于RS(255,223)码编/译码器。  相似文献   

16.
The implementation of a FIR filter using a new hybrid RNS-binary arithmetic is presented for the first time. In the new arithmetic, the data samples are represented using RNS, and hence the carry free advantage of RNS computations is retained. However, the computation performed for each modulo is implemented using conventional binary arithmetic elements which overcome the drawback of ROM-based RNS arithmetic elements that become inefficient for large moduli. The conventional binary arithmetic elements are also faster and require less area than existing memoryless RNS arithmetic elements. It is shown that the filter structures based on the new arithmetic have better performance than those based on either the conventional binary or conventional RNS arithmetic for large moduli.  相似文献   

17.
The ability of monitoring the chip temperatures of power semiconductor modules at all times under various realistic working conditions is the basis for investigating the limits of the maximum permissible load. A novel transient thermal model for the fast calculation of temperature fields and hot spot temperature evolution presented recently is extended to include time-dependent boundary conditions for variations of ambient temperature and surface heat flows. For this a Green's function representation of the temperature field is used. Also, general initial temperature conditions are included. The method is exemplified by application to a dc/ac converter module for automotive hybrid drives. The thermal model, which can be represented by a thermal equivalent circuit, then is combined with an electrical PSpice-metal-oxide semiconductor field-effect transistor (MOSFET) model to allow for the fully self-consistent electrothermal circuit simulation of 42-V/14-V dc/dc-converter modules. 670 converter periods with altogether 8000MOSFET switching cycles in the six-chip module can be simulated within 1-h computing time on a Pentium PC. Various simulation results are presented, which demonstrate the feasibility of the simulation method and allow for the optimization of converter losses. Short circuit modes of converter operation are investigated with a high temperature increase also revealing the thermal interaction between different chips.  相似文献   

18.
Drolet  G. 《Electronics letters》1999,35(5):368-369
The multiplication, inversion, division and exponentiation of elements of GF(2m) are easily implemented with conventional arithmetic and logical units when the elements are in the logarithmic representation. An electronic architecture for the addition of two elements in the logarithmic representation is presented. The architecture of the adder is similar to that of the Massey-Omura multiplier for the normal basis representation. In particular, the same combinatorial circuit is used to successively compute every bit of the sum  相似文献   

19.
A circuit model of the Gunn device that retains both the time dependent and nonlinear device properties is presented. The model is based on the physical properties of a high-field domain in a uniformly doped sample and represents this domain and the remainder of the device by appropriate circuit elements. A computer program has been written that allows the device to be connected to any combination of RLC elements up to and including two parallel RLC circuits in series. Computer calculations have been made with a low resistance series circuit to simulate the Gunn mode of operation. The variation of Gunn frequency with bias voltage has been calculated and is in qualitative agreement with experiments. An inductance of 1 nH in series with 1 ohm is found to significantly alter results in comparison with the pure resistive case. The effect of this series inductance has also been observed experimentally as a lack of harmonics in resistive device mounts with stray inductance. Results obtained with a parallel RLC circuit point out the importance of circuit voltage control on the domain behavior. The LSA diode is treated as a bulk conductance following the drift velocity-electric field curve for GaAs. The bulk velocity and differential mobility are approximated by polynomials of electric field from which the device equivalent circuit is obtained. A physical insight into the operation of the LSA device is gained through a plot of time-integrated differential mobility with time. It is shown that an RF load for which this integral does not change appreciably over an RF period results in maximum efficiency. Results of efficiency and negative resistance of the device obtained for a bias field of 10 kV/cm are presented and are in good agreement with calculations of other workers.  相似文献   

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