An analytical parasitic resistance dependent Id–Vd model for planar doped InAlAs/InGaAs/InP HEMT using non-linear charge control analysis

An analytical parasitic resistance dependent model for the current voltage characteristics for InAlAs/InGaAs/InP HEMT is proposed. The model uses a new polynomial dependence of sheet carrier concentration on gate voltage to calculate I_d–V_d characteristics and has been extended to obtain transconductance, output conductance and cut-off frequency of the device. A maximum cut-off frequency of 83 and 175 GHz was obtained for channel length of 0.25 and 0.1 μm, respectively. Close agreement with published results confirms the validity of our approach.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

Model Development for Current–Voltage and Transconductance Characteristics of Normally-off AlN/GaN MOSHEMT

In this paper, an AlN/GaN-based MOSHEMT is proposed, in accordance to this, a charge control model has been developed analytically and simulated with MATLAB to predict the characteristics of threshold voltage, drain currents and transconductance. The physics based models for 2DEG density, threshold voltage and quantum capacitance in the channel has been put forward. By using these developed models, the drain current for both linear and saturation models is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness which builds up the foundation for enhancement mode MOSHEMT devices. The predicted I_d–V_gs, I_d–V_ds and transconductance characteristics show an excellent agreement with the experimental results and hence validate the model.     

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substratesfor future high power RF applications

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al₂O₃ passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance g_m of 1050 mS/mm, current gain cut-off frequency f_t of 350 GHz and power gain cut-off frequency f_max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density (n_s) and breakdown voltage are 1580 cm²/(V·s), 1.9×10¹³ cm^-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.     

20-nm enhancement-mode metamorphic GaAs HEMT with highly doped InGaAs source/drain regions for high-frequency applications

In this article, the DC and RF performance of a SiN passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with highly doped InGaAs source/drain (S/D) regions have investigated using the Synopsys TCAD tool. The 20-nm enhancement-mode (E-mode) MHEMT device also features δ-doped sheets on either side of the In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As channel which exhibits a transconductance of 3100 mS/mm, cut-off frequency (f_T) of 740 GHz and a maximum oscillation frequency (f_max) of 1040 GHz. The threshold voltage of the device is found to be 0.07 V. The room temperature Hall mobilities of the 2-dimensional sheet charge density are measured to be over 12,600 cm²/Vs with a sheet charge density larger than 3.6 × 10¹² cm^?2. These high-performance E-mode MHEMTs are attractive candidates for sub-millimetre wave applications such as high-resolution radars for space research, remote atmospheric sensing, imaging systems and also for low noise wide bandwidth amplifier for future communication systems.     

A modified model for Si/SiGe MOS-gate delta-doped HEMTs

An analytical model for threshold voltage (V_th) and minimum gate voltage (V_tl) of Si/SiGe MOS-gate delta-doped HEMT is presented in this letter. The model is valid for any width of the delta-doped layer and any distance of the layer from the Si/SiO₂ interface. Using the model, V_th and V_tl of a Si/SiGe MOS-gate delta-doped HEMT of known dimensions are calculated. To investigate the effect of variation of the width of the delta-doped layer, the threshold voltage and the minimum gate voltage have been plotted against the width. Medici™ simulation have been performed on the same device to evaluate V_th and V_tl for different delta-doped layer widths. The simulation results are in good agreement with the results found using the analytical model.     

Ion-implanted microwave field-effect transistors in GaAs

Microwave field effect transistors have been fabricated in gallium arsenide by using sulfur ion implantation directly into semi insulating Cr doped substrates to produce the channel region, eliminating the need for growth of an epitaxial layer. This implantation method has been used to produce 0·25 μm thick, n-type layers with uniform thickness and carrier concentration, and carrier mobility ranging from 2410 to 3620 cm²/V sec in different samples. Because of the uniformity, FET's fabricated in these layers have exhibited reproducibility of transconductance and pinchoff voltage from device to device on a wafer to better than ±10 per cent. Cr doped GaAs of commonly available quality was found to be satisfactory for FET fabrication, although minimum Cr compensation is desirable to obtain highest mobility. S parameter measurements of microwave characteristics indicated a projected f_max = 20 GHz but transducer gain cutoff occurred at approximately 7 GHz because of impedance mismatch and package parasitics.     

Characterization of selective reactive ion etching effects on delta-doped GaAs/AlGaAs MODFET layers

The effects of selective reactive ion etching (SRIE) using SiCl₄/SiF₄ plasma on delta-doped GaAs/Al_0.3Ga_0.7As modulation-doped field-effect transistor (MODFET) structures and devices have been investigated. The results are compared with those of corresponding conventionally doped MODFETs. Hall measurements were conducted at 300 and 77 K to characterize the change in the transport properties of the two-dimensional electron gas due to low energy ion bombardment during the SRIE process. Delta-doped structures showed a smaller change in sheet carrier density and mobility compared to conventionally doped structures. Direct current and high frequency measurements were performed on the SRIE gate-recessed MODFETs. No significant change in threshold voltage was observed for the delta-doped MODFETs in contrast to an increase of about 300 mV for the conventionally doped MODFETs processed at a plasma self-bias voltage of −90 V and a 1200% overetch time. Maximum dc extrinsic transconductance and unity current gain cutoff frequency did not change with SRIE processing for either of the structures. This paper was presented at the Electronic Materials Conference at MIT, Cambridge, 1992.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.