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1.
该文讨论了行波管多级降压收集极CAD理论模型,在二维轴对称条件下,对网格自动划分技术、二次电子发射模型、空间电荷效应计算方法、外加磁场影响、收集极效率计算方法等进行了深入研究,并在现有模型基础上进行了修改,以获得更好的模拟效果.同时在此基础上,开发了行波管多级降压收集极CAD软件UESTC MDC,并对该软件的使用进行了简单的介绍.最后根据国外研究发展动向,对我国行波管多级降压收集极CAD软件的发展提出了一些可参考的意见和建议.  相似文献   

2.
马亚林  赵亚林  徐寒  周在进   《电子器件》2007,30(4):1279-1284
文中较全面地讨论了多级降压收集极的物理模型.借助Orion(2.5维)软件设计出效率较高的带有再聚焦系统的四级降压收集极,并考虑了次级电子的影响,模拟计算多级降压收集极和再聚焦区的性能,为行波管整管效率的提高提供了保证.  相似文献   

3.
多级降压收集极CAD中的二次电子发射模型   总被引:2,自引:0,他引:2  
多级降压收集极被广泛应用于提高微波放大器件效率.多级降压收集极中的二次电子发射对其效率有重要影响.该文探讨了真二次电子、弹性反射电子、非弹性反射电子3种二次电子发射模型,对发射率、发射角度以及能量分布情况进行了深入分析,并对考虑二次电子后的收集极模拟计算收敛条件进行了讨论.上述结果在多级降压收集极CAD软件中得到应用,定量分析了其对多级降压收集极效率的影响.  相似文献   

4.
多级降压收集极中次级电子的研究   总被引:5,自引:0,他引:5  
效率与电子回流率是考核多级降压收集极的重要指标,而多级降压收集极中次级电子的存在对效率和电子回流率有重要影响.因此,对次级电子的研究有重要意义.本文探讨了次级电子发射的物理原型,并根据其编制了相应的CAD程序, 在对多级降压收集极的试算中,取得了较好的效果.  相似文献   

5.
多级降压收集极被广泛地应用于空间行波管的设计中,本文介绍了一种四级降压收集极的设计和模拟方法。通过对某一空间行波管互作用后的废电子注信息进行分析,得到电子注在收集极的入口条件,并且根据电子注入口条件确定各电极的电位,用行波管模拟软件模拟废电子注在收集极内的发射情况,计算出收集极的效率,通过分析电子注粒子运行轨迹和能量分布,优化收集极边界条件和各电极电位设置,提高收集极效率,降低电子回流率。结果表明:利用此方法计算得到的收集极效率达到80%以上,该模拟分析方法对行波管收集极的研究设计具有参考价值。  相似文献   

6.
在美国空军(USAF)——国家航宇局(NASA)共同制定的规划中,Lewis研究中心正在进行电子对抗行波管效率的改进工作,它是通过采用多级降压收集极(MDC)以及在该中心所探索的对耗能电子注的再聚焦技术来实现的。在本规划的分析阶段,计算了整个行波管的三维电子注轨迹。轨迹计算一直到耗能电子注的再聚焦区和降压收集极。对收集极效率、收集极损耗和管子总效率进行了验证和计算。在实验工作方面,首先对不用多级降压收集极的管子性能进行估测,然后对耗能电子注的对称性、圆度和速度离散作了分析。最后,装上了多级降压收集极,使其性能最佳并进行了估测。对于理想的行波管,三维理论表明:具有对称、圆型并有最佳再聚焦电子注的2级多极降压收集极在中心频带有81%的效率(多级降压收集极),而4级多级降压收集极有85%的效率。实验结果所获得的数据表明:一个倍频程带宽——(4.8~9.6)千兆赫、功率为330~550瓦行波管的2级和4级降压收集极的最小多级降压收集极效率分别为81%和83%。  相似文献   

7.
介绍了未来星际通讯用Ka波段30W空间行波管的最新研究进展。行波管电子枪采用传统的皮尔斯型电子枪,高频结构采用螺旋线慢波结构和品型夹持结构,为了保证较高的收集极效率,采用四级降压收集极。测试结果表明在工作频带内行波管输出功率超过34.6W,总效率超过47.5%。当行波管工作于低频状态时,行波管总效率超过了50%,已达到目前国外同等功率量级Ka波段空间行波管研究水平。  相似文献   

8.
微波管中收集极要受到电子束轰击而发热,如果散热不及时,会出现收集极内表面熔蚀。收集极的散热问题、绝缘问题以及降压问题要同时考虑。降压收集极组件如果装配不紧密,收集极散热的效果就变差,导致大量放气,整管寿命缩短;挤压过紧则容易使陶瓷材料断裂,导致收集极的绝缘、耐压性能变差。运用国际上先进的磁脉冲挤压法技术,经过30多次试验,成功组合各类降压收集极40只。采用这种新工艺完全能够解决降压收集极组合的问题。  相似文献   

9.
行波管多级降压收集极的计算和实验研究   总被引:3,自引:1,他引:2  
任渠江  廖复疆 《电子器件》1999,22(3):149-156
采用多级降压收集极是提高行波管效率析有效途径之一。本文在SLAC-266程序的基础上对一支带有二级降压收集极的国外行波管进行了计算,并且将计算结果同实验结果进行了比较。同时用电子注分析仪对降压收集极区电子注和纵向速度分布进行了实验研究,获得了该二级降压收集极的部分工作曲线,并对实验结果进行了分析讨论。  相似文献   

10.
效率是行波管(TWT)的重要技术指标,为提高某一0.22 THz折叠波导行波管的效率,需设计多级降压收集极。对注波互作用后的电子注信息进行分析,估算收集极效率最高时的电压设置。利用电磁仿真软件对三级降压收集极电极结构和电压设置进行仿真优化,得到效率大于87.5%,回流电流小于0.328 9 mA的轴对称三级降压收集极;在第二电极入口采用斜口结构进行仿真优化,得到回流电流小于0.075 mA的非轴对称三级降压收集极。结果表明,采用斜口结构可以有效降低0.22 THz行波管多级降压收集极的回流电流。  相似文献   

11.
目前行波管正朝着小型化、大功率以及高频率三个方向发展。对行波管的收集极进行一维或者多维尺寸的非对称改进是行波管小型化的重要途径。椭圆收集极相对传统圆收集极具有内表面面积大、一维尺寸小等优点,是一种非常可取的收集极形状。根据轴对称电场几何相似性定理,在收集极入口通过类似四极透镜作用将圆柱型电子注压缩成为类椭圆形电子注,更利于椭形收集极对电子的回收。利用计算机辅助设计软件对重新设计的行波管椭圆收集极进行仿真,为非对称收集极设计提供参考[1]。  相似文献   

12.
A new design concept for bipolar integrated circuits with high functional density will be presented. The basic current hogging injection logic (CHIL) gate consists of a lateral intermediate collector structure, where the last collector simultaneously forms the base region of an inversely operated vertical output transistor. Thus a CHIL gate can be looked at as a CHL gate with a functionally integrated output transistor, or as an integrated injection logic (I/SUP 2/L) inverter with controlled injection. Dc and pulse measurements are discussed and calculated results with a simple model suitable for computer-aided design (CAD) are presented. The static noise immunity of CHIL circuits is compared to CHL and I/SUP 2/L. CHIL circuits are well suitable for large-scale integration (LSI) and are technologically compatible to all circuits fabricated in a standard buried collector (SBC) process.  相似文献   

13.
丁晟 《电子器件》2012,35(2):139-141
简要介绍了Ku波段高效率脉冲行波管的设计、CAD计算和测试结果。通过对电子枪、聚焦系统、慢波电路、电子注和慢波线高频场大信号互作用的计算、收集极的设计,获得了符合新雷达系统技术指标要求的整管。实测结果为:在Ku波段2 GHz频带范围内,等激励、脉冲输出功率大于2.2 kW、效率大于30%。  相似文献   

14.
采用了CST工作室套装TM电磁仿真软件对一个典型的Ku波段螺旋线行波管的电子枪、磁聚焦系统、慢波结构和注一波互作用的非线性过程进行了三维的静电场、静磁场、粒子跟踪、本征模、粒子模拟的仿真和分析,得到了该行波管电子枪导流系数、慢波结构冷测特性以及输出功率和增益等参数,仿真所得数据与实测数据相符,证明了三维数值仿真全管的可行性,为后期设计和优化奠定基础。  相似文献   

15.
A Gummel-Poon model is developed for ZnSe-Ge-GaAs heterojunction bipolar transistors (HBTs). In this structure, undoped Ge spacers are placed at the emitter-base and collector-base junctions. Injected current components as well as bulk, spacer, and space charge recombination current components are modeled. Early voltage and bandgap narrowing effects are included in the model. The device performance was simulated and compared with the experimental results. The paper shows a good agreement between our model and the experimental results. The paper shows also that using spacers would improve the device performance. The advantages of this model is that it is analytical, compact, and can be easily implemented in CAD tool programs to simulate single or double HBTs with similar or dissimilar materials structure for the emitter and collector.  相似文献   

16.
Double-heterojunction bipolar transistors (DHBT) can exhibit a large collector/emitter offset voltage at zero collector current which will adversely affect digital switching circuits. It is shown that this effect results from insufficient grading at the base/collector heterojunction. A GaAlAs/GaAs DHBT grown by MBE having a 130 ? compositional grading at the emitter/base and base/collector junction showed no sign of the collector/emitter offset voltage.  相似文献   

17.
InGaP/GaAs heterojunction bipolar transistors with various collector structures are compared. The dependence of d.c. device characteristics on the thickness of the n GaAs spacer in the collector of composite collector devices is presented. Results indicate that the spacer thickness significantly affects the performance of the transistor. An n+ doping spike on the InGaP side of the collector heterojunction is included in the collector design of the composite collector devices. Standard single-heterojunction d.c. results are compared to abrupt double- and composite collector heterojunction devices. Optimization of the spacer thickness, in conjunction with the n+ doping spike, eliminates most of the detrimental effects associated with a double-heterojunction device while retaining the beneficial properties of a wide-gap collector. As expected, the composite collector structure produces devices with higher breakdown voltages and lower offset voltages than single heterojunction devices. In addition, optimizing the spacer thickness can reduce the collector current saturation voltage of the composite collector device below that of a single-heterojunction device. These characteristics make composite collector heterojunction bipolar transistors ideal candidates for high power microwave device applications.  相似文献   

18.
A two-dimensional analysis of high-level transistor operation is presented which includes the effects of an extended base region, internal emitter biasing, γ-falloff, unequal collector and emitter dimensions, and surface recombination. The transistor model considered is directly appropriate to the strip-type geometry, but also yields results which are approximately valid for the ring-and dot-type structures under certain conditions. Transforming the geometry permits a solution to be obtained for the charge-density distribution in the base as well as the current density distribution at the emitter and collector junctions. From these relations, both the collector and emitter transport (diffusion) capacitances are also determined. Two complete numerical evaluations of the theoretical results are given, first for a symmetrical unit with equal emitter and collector dimensions, and second for an unsymmetrical unit with the collector dimension 24 per cent greater than that of the emitter. It is indicated that an appreciable fraction of the total base charge can exist external to the emitter and collector, particularly for very high-level operation, causing large increases (1.5 to 3 times the one-dimensional values) in both the emitter and collector transport capacitances, particularly for units having grossly extended base regions and low surface-recombination velocities. Further shown is the effect of increasing the collector dimension over that of the emitter; the capacitances are appreciably lowered and the transport efficiency (and thus the current gains) is increased. Finally, some collector transport capacitance measurements are presented covering the entire operating range which tend to substantiate the theoretical results.  相似文献   

19.
郑志清  罗勇 《现代电子技术》2012,35(23):178-180
为了确定回旋行波管收集极入口的初始条件,利用CST2009模拟回旋行波管静态电子的运动轨迹,以3D模型,更直观、形象的显示出电子在回旋行波管中的运动轨迹。模拟计算表明,在电子注电压为70kV,电子注电流为10.4A,工作磁场为l.5T时,回旋行波管的电子注发射出的电子最终降落在收集极的530~700mm处。模拟结果为回旋行波管的设计和收集极的热分析提供了有效的依据。  相似文献   

20.
A ten-stage electrostatic depressed collector, designed with the aid of an analog computer, was tested on a 1-kW CW 750-MHz klystron. Excellent correlation was achieved between computed and measured performance under varying conditions of RF drive. At full RF power output approximately 60 percent of the spent beam energy was recovered by use of the depressed collector. The net power conversion efficiency of the tube was raised from its undepressed value of 54.3 percent to approximately 70.9 percent. At one-half full power output, a collector efficiency of 70 percent was measured. At zero RF power output collector efficiency was 80 percent. To achieve these results it was necessary to install a small focusing coil between the final drift tube and the collector. No spurious oscillations or instabilities were detected when collector depression was employed, nor was electron backstreaming increased significantly. Intentional short circuiting of adjacent collector electrode pairs was shown to cause only minor degradation in collector performance.  相似文献   

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