A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

基于FPGA的大面阵CMOS相机高速率电子学系统设计

目前深空遥感探测多采用CCD作为高分辨率相机的传感器,相较于CCD,面阵CMOS驱动更简单、功耗更低、抗辐射能力更强,是深空遥感探测目前的发展趋势。为此,本文基于CMOSIS公司生产的型号为CMV20000,图像分辨率为5 120×3 840的CMOS探测器,设计完成了一个大面阵CMOS高分辨率相机,图像分辨率为5 120×3 840。详细阐述了以FPGA为核心的电子学系统的整体结构,结合CMV20000的工作模式和时序电路,实现了高分辨图像的高速传输以及数据校正。试验结果表明,设计的相机系统方案合理,解决了CMV20000数据无法对齐的数据校正问题,系统运行稳定可靠,安装光学系统后能够获取高质量图像。     

CMOS图像传感器片上系统及其在手机上的应用

带相机功能的手机越来越流行并逐渐成为手机的标准配置。CMOS图像传感器因其在低成本、图像效果好、低功耗、集成度高等方面的优势,在手机市场上逐渐成为主流。随着功能与集成度的提高,片上系统与单芯片方案已经成为一个趋势。介绍CMOS图像传感器片上系统的架构与原理、图像信号处理模块,然后给出他在手机系统上的应用与软件实现。     

Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-mum CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology     

用于低噪声CMOS图像传感器的流水线ADC设计及其成像验证

在对低噪声CMOS图像传感器的研究中,除需关注其噪声外,目前数字化也是它的一个重要的研究和设计方向,设计了一种可用于低噪声CMOS图像传感器的12 bit,10 Msps的流水线型ADC,并基于0.5μm标准CMOS工艺进行了流片。最后,通过在PCB测试版上用本文设计的ADC实现了模拟输出的低噪声CMOS图像传感器的模数转换,并基于自主开发的成像测试系统进行了成像验证,结果表明,成像画面清晰,该ADC可作为低噪声CMOS图像传感器的芯片级模数转换器应用。     

基于日盲型AlGaN的紫外相机设计

在"日盲段"240～290 nm进行窄波段探测,具有背景干扰小的优势。相比于传统紫外探测器必须协同窄带滤光片工作,AlGaN具有固有窄波段控制和无需制冷两大优点。介绍了基于日盲型AlGaN焦平面器件的紫外相机的软、硬件设计。紫外相机由紫外透射式光学系统,日盲型AlGaN器件,偏置电路及驱动电路,低噪声前放、数据处理及传输单元构成,核心器件AlGaN采用背照式PIN阵列通过铟柱倒焊于硅基电容反馈跨导放大器(CTIA)读出电路的结构。紫外相机的设计指标为:光学口径80 mm,焦距130 mm,像元尺寸50μm,瞬时视场0.4 mrad,总视场3°,积分时间可控,帧率最高可达100帧/s。经初步室内测试,效果良好,对发展日盲型面阵AlGaN应用平台做出了有意义的探索和研究。     

基于FPGA和MV—D1024E相机的图像采集系统

分析了MV—D1024E系列高帧频CMOS相机的工作时序和参数,阐述了CAMERA—LINK接口协议,并对高速数据流的存储与处理机制进行分析,利用FPGA实现了相机的数据接口和控制,并设计灵活的USB接口,利用PC机作为参数输入和显示界面,完成一个从图像采集到存储、显示的高帧频图像采集系统的设计。该系统可靠性好、集成度高、功耗低,且满足不依赖于PC机的图像采集系统的应用要求。     

Backside-illuminated lateral PIN photodiode for CMOS image sensor on SOS substrate

In this paper, we propose a method to design charge-sensing elements for CMOS image sensor pixels on a silicon-on-sapphire (SOS) substrate. To address the low quantum efficiency problem due to very thin active film used, a backside illuminated lateral PIN photodiode on an SOS substrate is proposed and developed. It has the advantages of higher photo response with a PIN structure and improved optical transmission with a backside illumination through a transparent sapphire substrate. An active pixel sensor (APS) based on the PIN and backside illumination has been implemented in a commercially available SOS CMOS process. Acceptable sensitivity in optical conversion from the APS can be achieved, even with the ultrathin silicon film. The APS is demonstrated to function at 1.2 V, giving a dynamic range of 51 dB.     

Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera

A low-power, large-scale parallel video compression architecture for a single-chip digital CMOS camera is discussed in this paper. This architecture is designed for highly computationally intensive image and video processing tasks necessary to support video compression. Two designs of this architecture, an MPEG2 encoder and a DV encoder, are presented. At an image resolution of 640 × 480 pixels (MPEG2) and 720 × 576 (DV) and a frame rate of 25 to 30 frames per second, a computational throughput of up to 1.8 billion operations per second (BOPS) is required. This is supported in the proposed architecture using a 40 MHz clock and an array of 40 to 45 parallel processors implemented in a 0.2 m CMOS technology and with a 1.5 V supply voltage. Power consumption is significantly reduced through the single-chip integration of the CMOS photo sensors, the embedded DRAM technology, and the proposed pipelined parallel processors. The parallel processors consume approximately 45 mW of power resulting a power efficiency of 40 BOPS/W.     

基于相对比率的高帧频图像采集器设计与实现

为了在机器视觉应用中是实现高动态范围（high dynamic range,HDR）图像采集,提出了一种基于检测像素相对比率的新型图像采集系统。提出的图像采集器使用全差分电路检测信号比,由基于数字计数器的紧凑列并行读出电路捕捉像素的脉冲宽度调制输出。并设计了相应的光电流比检测像素方法,能独立地捕捉局部场景特征。实验结果显示提出的COMS图像传感器性能较好,当标称帧频为9600帧/秒时,提出的32×32像素阵列原型CMOS图像传感器消耗了4 mW的功率;当最大帧频为24000帧/秒时,此图像传感器消耗了6.8 mW的功率。     

低照度宽幅航空相机系统设计

为了满足低照度环境下航空影像信息快速获取的需求,对一种低照度宽幅成像系统进行了研究。基于相机摆扫成像的工作模式,明确了采用大相对孔径低畸变的光学系统,配合真空制冷的低噪声高灵敏度CMOS探测器成像,并通过高速振镜进行扫描像移补偿的技术路线。详细阐述了相机机械构型的设计思路,总结了一套可工程应用的低照度成像能力计算方法。研究了振镜补偿像移的基本原理,并对相机主体框架进行了仿真分析计算。依据该设计和研究结果,完成了低照度宽幅航空相机的加工装配。该相机具有0.1 m （航高1 km）地面像元分辨率, 成像照度适应范围为10~100000 lx,并且在速高比≤0.04时,可实现3倍航高的大收容宽度。系统的成像质量优良,实测镜头在77 lp/mm时,中心视场传递函数大于0.45。实验室和外场飞行试验所获取的图像清晰,对比度和分辨率高,可以满足使用需求。同时,该相机实际包络尺寸为190 mm×140 mm×140 mm,质量仅为2800 g,具有轻小型的特点。     

一种适用于目标快速定位和图像输出的有源图像传感器设计

提出了一种适用于目标快速定位和图像输出的有源图像传感器(Active Pixel Sensor,APS)的设计方案。与传统的图像传感器不同,这种传感器可以根据目标信号的位置进行区域图像输出,从而实现目标的快速定位和图像输出。阐述了这种传感器的区域划分原则和区域图像输出控制方法。通过设计和仿真测试一个48×48的面阵,验证了这种传感器的目标快速定位能力。测试结果表明,这种传感器的帧频比传统的传感器高4倍以上。     

低功耗CMOS视觉传感器新结构及其SOC实现

提出了一种新型单片CMOS摄像传感器电路的体系结构,该结构集成了摄像、噪声消除、模数转换、图像处理、图像增强、色彩空间转变等功能.采用该结构实现的CMOS视觉芯片动态范围大,在弱光和强光下均能拍摄图像;工作在30帧的情况下,消耗的功耗只有75 mW,具有低功耗的优点.基于该单芯片低功耗CMOS视觉传感器芯片开发的系统元器件少,可广泛应用于手机拍照、数码相机和网络视频等多媒体终端.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

A 640×512 CMOS image sensor with ultrawide dynamic rangefloating-point pixel-level ADC

Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640×512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-to-digital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sampling to enhance dynamic range. Since pixel values are available to the ADC's at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640×512 sensor is implemented in 0.35-μm CMOS technology and achieves 10.5×10.5 μm pixel size at 29% fill factor. Characterization techniques and measured quantum efficiency, sensitivity, ADC transfer curve, and fixed pattern noise are presented. A scene with measured dynamic range exceeding 10000:1 is sampled nine times to obtain an image with dynamic range of 65536:1. Limits on achievable dynamic range using multiple sampling are presented     

CCD区域倍频读出及其对成像的影响

在某空间项目中,需要使用一款指定的CCD传感器研制一套用于空间成像的CCD摄像机系统,并且要求图像的帧频高于CCD传感器的标准帧频。简单的超频读出CCD会使摄像机的信噪比下降。文中首先分析了CCD摄像机在空间条件下影响成像信噪比的多种原因,发现读出噪声对输出图像的信噪比影响是最大的。使用区域倍频读出方法来提高CCD摄像机的输出帧频,即在图像的水平和垂直方向都使用4倍的时钟读出部分像元。最后把区域倍频读出CCD的图像信号和整体超频读出CCD的图像信号进行了信噪比对比检测,测试结果表明区域倍频读出的CCD图像质量较好。     

基于CMOS传感器的光ID信息服务系统模型

CMOS图像传感器具有功耗低、尺寸小,以及价格便宜等优点,目前已被广泛应用于智能手机中.采用CMOS图像传感器作为可见光通信的接收装置,有利于技术的推广和实用化.文章首先介绍了采用CMOS传感器作为可见光通信接收机的原理,接着针对当前国内外研究中存在的问题提出了信号增强算法,最后验证了算法的可行性和适用性,并由此提出了一套光ID信息服务系统模型.     

A log-polar image sensor fabricated in a standard 1.2-μm ASICCMOS process

A CMOS log-polar or foveated image sensor for use in mobile robotic and machine vision applications has been designed, fabricated, and tested. The sensor benefits from a high degree of integration, minimal power consumption, and ease of manufacture due to the use of a standard 1.2 μm ASIC CMOS process. The sensor is composed of two distinct CMOS imager arrays which together solve the problem of obtaining good image resolution over a wide field of view. With resolution sensing is accomplished with a 40×40 array of individual pixels each measuring 9.6 μm on a side. A wide field of view is provided by an array of 64×16 pixels arranged on a log-polar grid. The maximum measured dynamic range for the fabricated log-polar array is 46 dB, while the lowest observed fixed-pattern noise is 0.5% of saturation. Combined power consumption of both arrays is under 2 mW when operating from a single 5-V supply at a frame rate of 30 frames/s     

面阵CMOS图像传感器性能测试及图像处理

CMOS图像传感器具有驱动简单、单电源供电、集成度高、功耗低、抗辐射能力强等优点。但是在航天光学遥感领域,CMOS图像传感器应用还不普遍。在该领域亟需大规模、高读出速度、大动态范围的图像传感器,CMOS图像传感器LUPA4000正是这样一款高性能面阵图像传感器,因此,选择LUPA4000作为研究对象,对其缺陷像元、光响应非均匀性、信噪比等性能指标进行测试。测试结果表明存在缺陷像元数量多、光响应非均匀性较大、信噪比较低等问题。根据测试结果采用暗背景扣除、缺陷像元替换、非均匀校正三种方法进行图像处理。对每种方法单独处理和各种方法组合处理的处理效果从图像信噪比和成像图像质量两方面进行分析评估,结果表明:非均匀校正联合缺陷像元替换的处理方法处理效果最佳。     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.