Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications

This work presents a means to enhance the immunity of non-ideal opamp gain effect of the fourth order multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. The first stage of the SDM is a low-distortion single-loop second order SDM, while the second stage is a low-distortion interpolative second order SDM with Chebyshev type II filter technique. Theoretically, the conventional MASH SDM is impacted by the nonlinear finite gain of the operational amplifier. This impact may have two main phenomena. First, it leaks the incompletely corrected quantization error to the output. Secondly, the nonlinearity causes the harmonic distortion of the input signal. The proposed architecture can reduce the distortion and the sensitivity of the nonlinear finite opamp gain to improve the performance by using low-distortion technique in the MASH SDM. Furthermore, the lower power budget and simplified digital cancellation logic can be achieved. The experimental results indicate that the dynamic range (DR) can reach 87dB with power dissipation of 65 mW. A test SDM chip for Asymmetric Digital Subscriber Line (ADSL) application is designed and implemented by TSMC 0.25 um 1P5M process. Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan in 1983. In 1988, he received the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992, he received the Ph.D. degree in the electrical engineering from Texas A & M University, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently, he is a Professor and Department Chair of the Department of Electrical Engineering at Tamkang University. Dr. Chaings research interest includes computer arithmetic, computer architecture, digital signal processing for VLSI architecture, architecture for image data compressing, analog to digital data conversion, and low power circuit design. Hsin-Liang Chen was born in Taipei, Taiwan, in 1974. He received the B.S. degree and M.S. degree in the electrical engineering from Tamkang University, Taipei, Taiwan, in 1997 and 2003, respectively. He is currently working toward the Ph.D. degree at Tamkang University. His research interest focuses on mixed-signal CMOS circuit, sigma delta ADC, and low power circuit.     

A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at $-$0.12 dB From Full Scale Input

A second order sigma delta modulator (SDM) with a 5-bit quantizer has been presented using several novel techniques: simplified DAC arrays for easy implementation, high-order truncation noise shaping for increased tolerance to analog imperfections, and an extended dynamic range for a maximum input signal swing of up to $-0.12 ~{hbox {dB}}_{rm FS}$ (Full Scale). With truncation filters and a pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design, fabricated in a 0.18 $mu{hbox {m}}$ dual gate oxide (DGO) process obtains a signal-to-noise-and–distortion ratio (SNDR) of 105.9 dB and a dynamic range (DR) of 107.4 dB with 31.25-KHz bandwidth at an 8-MHz sampling frequency and a power consumption of 14.7 mW.      

Broad-band linearization of a Mach-Zehnder electrooptic modulator

Analog optical-link dynamic range in excess of 75 dB in a 1-MHz band has been achieved using specially designed electrooptic modulators that minimize one or more orders of harmonic and intermodulation distortion. To date, however, such “linearized” modulators have only enabled improved link dynamic ranges at frequencies below 1 GHz. Additionally, linearization across more than an octave bandwidth has required precise balancing of the signal voltage levels on multiple electrodes in a custom modulator, which represents a significant implementation challenge. In this paper, a link linearization technique that uses a standard Mach-Zehnder lithium-niobate modulator with only one RF and one dc-bias electrode to achieve broad-band linearization is discussed, resulting in a dynamic range of 74 dB in 1 MHz across greater than an octave bandwidth (800-2500 MHz). Instead of balancing the voltages on two RF electrodes, the modulator in this new link architecture simultaneously modulates optical carriers at two wavelengths, and it is the ratio of these optical carrier powers that is adjusted for optimum distortion canceling. The paper concludes by describing a second analogous link architecture in which it is the ratio of optical power at two modulated polarizations that is adjusted in order to achieve broad-band linearization     

A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications

The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. In multi-standard design, sigma-delta based ADC is one of the most popular choices. To this end, in this paper we present cascaded 2-2-2 reconfigurable sigma-delta modulator that can handle GSM, WCDMA and WLAN standards. The modulator makes use of a low-distortion swing suppression topology which is highly suitable for wide band applications. In GSM mode, only the first stage (2nd order ∑-Δ ADC) is used to achieve a peak SNDR of 88dB with over-sampling ratio of 160 for a bandwidth of 200KHz and for WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in the first stage and 2-bit in the second stage to achieve 74 dB peak SNDR with over-sampling ratio of 16 for a bandwidth of 2MHz. Finally, a 2-2-2 cascaded MASH architecture with 4-bit in the last stage is proposed to achieve a peak SNDR of 58dB for WLAN for a bandwidth of 20MHz. The novelty lies in the fact that unused blocks of second and third stages can be made inactive to achieve low power consumption. The modulator is designed in TSMC 0.18um CMOS technology and operates at 1.8 supply voltage.     

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

A third-order sigma-delta modulator with extended dynamic range

Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution analog-to-digital conversion in VLSI technology. Because high-order noise shaping greatly reduces the quantization noise in the signal band, the dynamic range of these modulators tends to be bounded by the thermal noise of the input stage and the maximum voltage swing in the signal path. This paper introduces a third-order cascaded sigma-delta modulator that uses a modified cascaded architecture and reduced gain in the first integrator to increase the dynamic range. An experimental modulator fabricated in a 1-μm CMOS technology attains a resolution of 17 b for a 25-kHz signal bandwidth while operating from a single 5-V supply. With an oversampling ratio of 128 and a clock frequency of 6.4 MHz, the modulator achieves a 104-dB dynamic range and a peak signal-to-noise+distortion ratio (SNDR) of 98 dB. As indicated by both measurements and simulations, the cascaded architecture also greatly reduces the discrete noise peaks that can be present in a single-stage architecture     

Designs of multi-bit sigma delta modulator

This paper presents new design variants of third order multi-bit sigma delta modulator (SDM): low distortion SDM and cascaded SDM. The proposed modulator based on the conventional SDMsuch L-0MASH(Multi-stAge noise SHaping) and interstage feedback topology. TheMASHSDM is not a single loop system. One of the drawback is that performance is limited by uncancelled noise from the first modulator and interstage feedback topology only cancels nonlinear errors introducing by multi-bitDACin the final stage, but the rest stage still containsDACnonlinearity errors without any noise shaping which still degrade overall system performance. An improved version of cascaded multi-bit SDM is proposed to overcome these problems mentioned above. In addition a third order low distortion SDM is also proposed. Simulation results verify the superiority of the both proposed modulator.     

A 5th-order ΣΔ modulator with combination of op-Amp and CBSC circuit for ADSL applications

In this letter, a 5th-Order single-loop low distortion Sigma–Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e−3.     

A New Multistage Noise-Shaping Architecture

This paper presents a new architecture for high dynamic range, low oversampling ratio (OSR) noise-shaped digital-to-analog converters (DACs). The instantaneous noise feedforward architecture is a multistage structure in which the instantaneous noise and gain/phase distortion in the first stage are cancelled by passing them through another converter and then subtracting them at the output after analog attenuation. The signal-to-noise-and-distortion ratio (SNDR) of a device using this architecture scales as the product of the first noise shaper's SNDR and the ratiometric precision of the attenuator technology. This new architecture was implemented by driving the bits of an existing DAC (with binary weighting) using specially generated digital signals. One set of experimental measurements demonstrates a spurious-free dynamic range (SFDR) performance of 83 dBc in a 125-MHz bandwidth centered at 325 MHz while using an OSR of only 4. A second set of experimental measurements produces an SFDR performance of 70 dBc in a 125-MHz bandwidth centered slightly above 1.3 GHz with an OSR of 16.     

A 0.5-V 90-dB SNDR 102 dB-SFDR audio-band continuous-time delta–sigma modulator

A 0.5-V high performance continuous-time one-bit delta–sigma modulator is reported for audio applications. High performance under this ultra-low supply is achieved by a feed-forward modulator architecture for reduced integrator swing, a special switched-capacitor-resistor feedback for less sensitivity to jitter noise, and a fast-settling fully differential amplifier. The synthesized modulator also has a high thermal-noise-limited SNR of 91 dB over a 20 kHz bandwidth. The 0.5-V fully-differential gate-input amplifier employs an adaptive common-mode feedback frequency compensation circuit, which leads to a robust modulator performance against process, supply voltage and temperature variations. Fabricated in a standard 0.13 μm CMOS process, the modulator achieves a spurious-free dynamic range (SFDR) of 101.9 dB and a signal-to-noise plus distortion ratio (SNDR) of 90 dB (A-weighted) over a 20-kHz signal bandwidth, with the latter being very close to the thermal noise limit. The modulator operates over a supply range from 0.4 to 0.75 V and a temperature range from −20 to 90°C.