基于间隔分组的TSV聚簇故障冗余结构

由于不成熟的工艺技术和老化影响,基于硅通孔(Through Silicon Via,TSV)的三维集成电路(Three-Di-mensional Integrated Circuit,3D IC)中易发生聚簇故障,而降低芯片良率.为修复TSV聚簇故障,本文提出基于间隔分组的故障冗余结构.通过间隔分组将聚簇的TSV故障分...     

三维集成TSV垂直开关研究

针对三维集成中的TSV垂直开关,提出了其阈值电压和漏极电流的解析模型。采用基于有限元法（FEM）的Sentaurus软件进行解析模型验证。分析了三维集成TSV垂直开关的优点以及不同尺寸的TSV高度、半径及氧化层厚度对TSV垂直开关的阈值电压及漏极电流的影响。结果表明：TSV高度对阈值电压无影响,漏极电流增大;TSV的直径的增大会导致阈值电压减小,漏极电流增大;TSV氧化层厚度的增大会导致阈值电压增大,漏极电流减小。并且有限元法仿真与解析模型计算的误差均小于10%,验证了该模型的准确性,为TSV垂直开关的应用提供了重要的理论依据。     

基于菱形分组器的TSV聚簇故障容错结构

基于硅通孔的三维集成电路具备低互连延时、高密度、低功耗等优势.然而,由于不成熟的工艺技术,TSV制造堆叠及芯片绑定过程容易引入微孔、泄漏等缺陷,造成TSV故障.并且,这些TSV故障易呈现聚簇分布,严重降低三维集成电路的良率.针对TSV聚簇故障,本文提出了一种新的基于菱形分组器的TSV聚簇故障容错结构.以菱形分组器将TSV蜂窝阵列划分为若干TSV组,为每组配置相应的修复资源,达到分散TSV聚簇故障后逐个修复的目的,并以数据选择器链共享修复资源.实验结果表明,本文结构针对聚簇或均匀分布的TSV故障修复率均达到了99%,远高于同类方法,良好适用于修复TSV聚簇及均匀故障.     

基于环形振荡器的TSV故障非接触测试方法

为避免传统的探针检测对硅通孔(TSV)造成损伤的风险,提出了一种非损伤的TSV测试方法.用TSV作为负载,通过环形振荡器测量振荡周期.TSV缺陷造成电阻电容参数的变化,导致振荡周期的变化.通过测量这些变化可以检测TSV故障,同时对TSV故障的不同位置引起的周期变化进行了研究与分析,利用最小二乘法拟合出通过周期来判断故障位置的曲线,同时提出预测模型推断故障电阻范围.测试结构是基于45 nm PTM COMS工艺的HSPICE进行设计与模拟,模拟结果表明,与同类方法相比,此方法在测试分辨故障的基础上对TSV不同位置的故障进行分析和判断,并能推断故障电阻范围.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

基于TSV的三维集成螺旋电感等效电路模型

基于硅通孔(TSV)技术,可以实现微米级三维无源电感的片上集成,可应用于微波/射频电路及系统的微型化、一体化三维集成。考虑到三维集成电路及系统中复杂、高密度的电磁环境,在TSV电感的设计和使用中,必须对其电路性能及各项参数指标进行精确评估及建模。采用解析方法对电感进行等效电路构建和寄生参数建模,并通过流片测试对模型进行了验证。结果表明,模型的S参数结果与三维仿真结果吻合良好,证实了等效电路构建的精确性。采用所建立的等效电路模型可以提高TSV电感的设计精度和仿真效率,解决微波电路设计及三维电磁场仿真过程中硬件配置要求高、仿真速度慢等问题。     

应用材料加快三维IC的TSV应用

应用材料公司正在努力加快TSVs（through—siliconvias穿透硅互连）的广泛应用。TSVs是一项正在快速发展的新工艺，它将集成电路垂直堆叠，在更小的面积上大幅提升芯片性能并增加芯片功能。消费者希望电子产品变得更快更小，TSVs对于满足这种需求至关重要，它能实现DDR4 DRAM存储器、未来通讯和移动因特网芯片等的应用。     

硅通孔TSV关键 降低成本和解决工艺路线

芯片工艺流程微缩和低介电值材料的限制,3D堆叠技术被视为能否以较小尺寸制造高效能芯片的关键,而硅通孔(TSV)可通过垂直导通整合晶圆堆叠的方式,达到芯片间的电路互连,有助于以更低的成本,提高系统的整合度与效能,是实现集成电路3D化的重要途径。未来,TSV的应用将取决于制造成本的进一步降低,业界对TSV发展途径的认识统一。     

类同轴TSV的高频电学模型与分析

类同轴硅通孔(TSV)是射频三维(3D)集成电路(IC)中常用的垂直互连传输结构。针对该结构提出了一套通用的电阻-电感-电容-电导(RLCG)寄生参数计算公式,以及对应的高频等效电路模型。寄生参数是结构尺寸和材料特性的函数,可以方便地用于预测电学性能。使用三维全波仿真软件对所提出的模型进行了高达100 GHz的仿真验证,并分析了模型的散射参数与结构尺寸之间的关系。最后提出了特征阻抗的计算和优化方法,该方法可以为类同轴TSV的参数的确定提供参考。     

三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。     

一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型

为准确描述锥形TSV通孔寄生电阻、电容、电感高频下MOS效应及其频变特性,本文首先推导出了锥形TSV通孔压控MOS电容的解析模型。其次基于修正后的双传输线寄生参数提取公式对锥形TSV通孔内寄生参数进行了提取。最终建立了一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型。通过仿真工具验证模型精度,结果显示：在100GHz频带内模型与仿真结果吻合度较高,可以准确描述高频下锥形TSV通孔内寄生参数的半导体物理特性及频变特性,可用来预测锥形TSV通孔的电学特性,对优化三维集成电路电学性能有一定指导意义。     

基于多种添加剂的TSV镀铜工艺研究

穿透硅通孔技术(TSV)是3D集成电路中芯片实现互连的一种新的技术解决方案,是半导体集成电路产业迈向3D封装时代的关键技术。在TSV制作主要工艺流程中,电镀铜填充是其中重要的一环。基于COMSOL Multiphysics平台,建立了考虑加速剂和抑制剂作用的硅通孔电镀铜仿真模型,仿真研究得到了基于硫酸铜工艺的最优电镀药水配方,并实验验证了该配方的准确性。     

3DIC集成与硅通孔(TSV)互连

介绍了3维封装及其互连技术的研究与开发现状,重点讨论了垂直互连的硅通孔（TSV）互连工艺的关键技术及其加工设备面临的挑战．提出了工艺和设备开发商的应对措施并探讨了3DTSV封装技术的应用前景。     

A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

In 3D ICs, through-silicon-vias (TSVs) can suffer from cross coupling if signal integrity is not considered during the design process. In this paper, coupling between TSVs is modeled, and a chip-scale TSV shielding scheme is presented. A geometric model is developed to estimate TSV coupling. The low complexity of the geometric model makes it practical for chip-scale shield placement optimization. Two shield placement algorithms are presented and compared to standard shield placement techniques that use a high complexity circuit model of coupling. Results show that our algorithms are able to reduce the total cross coupling in a layout on average 111%/129% more than standard methods.     

Clock Mesh Network Design with Through‐Silicon Vias in 3D Integrated Circuits

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.     

Air-gap-based RF coaxial TSV and its characteristic analysis

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.     

一种含有盐酸胍的新型TSV抛光液

本文中,对一种新型的含有盐酸胍的TSV抛光液在CMP(化学机械平坦化)中的性能进行了研究,该TSV抛光液是一种碱性抛光液,并且不含任何抑制剂。在抛光过程中,盐酸胍作为一种有效的表面复合单元,相对于铜和介质的去除速率,钛的去除速率是可以通过调节选择性来控制的。在TSV生产过程中对于表面蝶形坑的修正及得到好的表面平整度是有利的。本文主要研究了抛光液成分的作用机理以及盐酸胍在TSV抛光液中的巧妙应用。     

Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers.     

Collective laser‐assisted bonding process for 3D TSV integration with NCP

Laser‐assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single‐tier LAB process for 3D through‐silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single‐tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu‐Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.