Packaging design of wide-angle phased-array antenna for frequenciesabove 20 GHz

Mechanical aspects of a new phased-array antenna design with a scan angle of ±70 degrees are presented. New packaging concepts were needed to accomplish, an industry first, the fabrication of a 91-element 44-GHz transmit array. The array architecture uses one hybrid module per channel. The RF signal is radiatively coupled to the modules, eliminating RF connectors. Multilayer boards are used to distribute control signals and DC which are connected to each module with space-efficient elastomeric connectors. All connections are made during the assembly of the array without need for permanent bonding. The array is designed for a low conductive thermal impedance from the monolithic microwave integrated circuits (MMIC) chips to the back of the array, where the heat is removed by convection     

Evaluation of Power Conditioning Architectures for Energy Production Enhancement in Thermoelectric Generator Systems

A large-scale thermoelectric generator (TEG) system has an unbalanced temperature distribution among the TEG modules, which leads to power mismatch among the modules and decreases the power output of the TEG system. To maximize the power output and minimize the power conversion loss, a centralized–distributed hybrid power conditioning architecture is presented, analyzed, and evaluated for a TEG system. The novel architecture is a combination of a conventional centralized architecture and a fully distributed architecture. By using the proposed architecture, most of the harvested power is processed by the centralized stage while only the mismatched power among the TEG modules is processed by the distributed stages. As a result, accurate and distributed maximum-power-point tracking (MPPT) for each TEG module and single-stage power conversion between the modules and load can be achieved. It offers the benefit of implementing high MPPT efficiency and high conversion efficiency simultaneously. A 50-W TEG system composed of two TEG modules is built and tested. Experimental results show that the proposed hybrid power conditioning architecture generates up to 5% more energy for a temperature difference between the two modules of only 10°C.     

Radiating and scattering analyses of a slot-coupled patch antennaloaded with a MESFET oscillator

In this paper, radiating and scattering analyses of a slot-coupled patch antenna loaded with a MESFET oscillator at free-running and injection-locked states are presented. This arrangement is a basic module of an injection-locked active array. With a small injection signal applied directly to the oscillator in a transmission-type mode or indirectly through a patch antenna to the oscillator in a reflection-type mode, the oscillator loaded antenna then becomes an injection-locked active antenna (ILAA) within the locking range. Simulation results yield the oscillating frequency and radiating power at the free-running state and the locking range and radiating power at the injection-locked state. Both radiating and scattering analyses are performed in a unified approach for the transmission-type and reflection-type operation modes of ILAA. Experiments show the validity of the developed theoretical analyses. These results can be applied in the ILAA array design     

Static and dynamic finite element modelling of thermal fatigue effects in insulated gate bipolar transistor modules

The aim of this paper is to demonstrate the use of finite element techniques for modelling thermal fatigue effects in solder layers of insulated gate bipolar transistor (IGBT) – modules used in traction applications. The three-dimensional models presented predict how progressive solder fatigue, affects the static and dynamic thermal performance of such devices.Specifically, in this paper, the analysis of an 800 A–1800 V IGBT module is performed. In the first part, the static analysis is realised. The parameters assessed are thermal resistance, maximum junction temperature and heat flux distribution through the different layers comprising the module construction. In the second part of the paper, transient analyses are performed in order to study the dynamic thermal behaviour of the module. The constructed thermal impedance curves allow for calculation of the device temperature variations with time. Stress parameters, such as temperature excursion and maximal temperature at chip and solder interfaces, are determined. Calibration of all simulation models is achieved by comparison with alternative theoretical calculations and manufacturers’ measured values provided in the data sheet book.     

Advances in Scanning Reflectarray Antennas Based on Ferroelectric Thin-Film Phase Shifters for Deep-Space Communications

Though there are a few examples of scanning phased array antennas that have flown successfully in space, the quest for ldquolow costrdquo high-efficiency large-aperture microwave phased arrays continues. Fixed and mobile applications that may be part of a heterogeneous exploration communication architecture will benefit from the agile (rapid) beam steering and graceful degradation afforded by phased array antennas. The reflectarray promises greater efficiency and economy compared to directly radiating varieties. Implementing a practical scanning version has proven elusive. The ferroelectric reflectarray, under development and described herein, involves phase shifters based on coupled microstrip patterned on films that were laser ablated onto substrates. These devices outperform their semiconductor counterparts from X- through and K-band frequencies. There are special issues associated with the implementation of a scanning reflectarray antenna, especially one realized with thin-film ferroelectric phase shifters. This paper will discuss these issues, which include relevance of phase shifter loss; modulo 2 effects and phase shifter transient effects on bit error rate; scattering from the ground plane; presentation of a novel hybrid ferroelectric-semiconductor phase shifter; and the effect of mild radiation exposure on phase shifter performance.     

Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.     

Dipole printed array antennas for mobile radio systems

Dipole array antennas realized on the basis of radiating modules in which strip dipoles are integrated with antenna balancers of a novel structure are described. Units with reduced overall dimensions and a reduced mass, which allow substantial simplification of the construction of array antennas for mobile radio systems, are proposed.     

一种基于AND-LUT的混合FPGA结构

提出了一种混合FPGA新结构--新颖的AND-LUT阵列结构.其创新之处在于由可编程逻辑簇(Cluster)和相关的连接盒(CB)组成的可编程逻辑单元片(Tile)可以根据应用需要灵活地配置成PLA或LUT,前者较适合于高扇入逻辑,后者较适合于低扇入逻辑.因此,结合两者优点的新颖AND-LUT阵列结构在实现各种输入的用户逻辑时都能保持很好的逻辑利用率.MCNC电路测试结果进一步表明,同一逻辑电路在文中提出的混合FPGA新结构中实现与在基于LUT的对称FPGA结构中实现相比,面积平均可节省46%,因而大大提高了FPGA器件的逻辑利用率.     

一种基于AND-LUT的混合FPGA结构

提出了一种混合FPGA新结构--新颖的AND-LUT阵列结构.其创新之处在于由可编程逻辑簇(Cluster)和相关的连接盒(CB)组成的可编程逻辑单元片(Tile)可以根据应用需要灵活地配置成PLA或LUT,前者较适合于高扇入逻辑,后者较适合于低扇入逻辑.因此,结合两者优点的新颖AND-LUT阵列结构在实现各种输入的用户逻辑时都能保持很好的逻辑利用率.MCNC电路测试结果进一步表明,同一逻辑电路在文中提出的混合FPGA新结构中实现与在基于LUT的对称FPGA结构中实现相比,面积平均可节省46%,因而大大提高了FPGA器件的逻辑利用率.     

Design and Characterization of Solid-State LDMOS Based T/R Module

Solid-state transmit/receive modules (T/R) are the vital super components of the multifunction Active Phased Array Radars. The Active Phased Array Radar consists of several solid-state T/R module to achieve the required power aperture product. This paper describes the realization of S-band dual T/R module. The research consists of design, modelling, analysis challenges, realization, and characterization. Studied several solid-state devices such as silicon bipolar junction transistors moving on to laterally diffused metal oxide semiconductor (LDMOS). The study eventually overtaken by the advancement in gallium arsenide and gallium nitride. The LDMOS devices are designed to handle the required power and could support up to a 20% duty cycle. Based on commercial off-the-shelf devices, we have studied, analyzed their performance, presented trade-offs between different performance parameters, and proposed a common arm architecture for a set of requirements. Dual T/R modules consist of two identical TRMs having two independent RF antenna connectors and a common RF input/output connector. A detailed methodology and step-by-step results were presented for developing S-band T/R modules for multi-function Active Phased Array Radar applications.

     

High-speed CMOS adder and multiplier modules for digital signalprocessing in a semicustom environment

For the realization of digital filters in a semicustom environment, high-performance adder and multiplier modules have been developed. These modules define the performance limits for digital finite impulse response (FIR) filters. The Gate Forest semicustom environment is a sea-of-gates-type transistor array. It supports the implementation of dynamic (domino) CMOS logic circuits. The circuit-design technique is applicable to compact high-speed designs. The realized dynamic adder architecture consists of a 2-b group adder and a Manchester carry chain (MCC). For an N-b addition this results in a N/2-b carry lookahead path. This dynamic adder scheme can be expanded into 4-b group adder modules. The multiplier module is a combination of a modified Booth-coded static adder array with a final dynamic MCC adder. The multiplier is clocked with a single (symmetric) clock signal. The clock signal is divided into a precharge pulse, in which the static part of the multiplier added array is evaluated, and an evaluation phase for the generation of the multiplication result (least significant bits). A 16-b×16-b multiplier based on this architecture runs with a 40-MHz system clock. The first chips have been processed in a 2-μm CMOS double-metal technology     

基于旋转矢量法的有源相控阵天线中场测量

中场测量技术所需设备量较少,成本较低,而旋转矢量法利用相控阵天线本身的波控系统测量阵面的幅相分布。两种测量各有优缺点,将这两种方法结合起来,可实现对有源相控阵天线的TR组件监测和相控阵天线的阵面幅相测量。与近场测量相比,该方法简单易行,可以实现有源相控阵天线的定期监测和校正,同时,对测量中的误差进行了分析,并提出了解决办法。     

Networked multimedia: the Medusa environment

The Medusa project at Olivetti Research aims to provide a networked multimedia environment in which many streams of multimedia data, perhaps thousands, are active simultaneously. Medusa uses a peer-to-peer architecture to control networked multimedia devices. In the software model presented to the applications programmer, active objects called modules represent cameras, displays, format converters, and so on. Data flows from module to module through connections between them, with proxy modules to restrict access for security reasons. The Medusa project is based on hardware that is a collection of asynchronous transfer mode (ATM) direct peripherals, including cameras, audio systems, multimedia storage servers, LCD displays, and televisions, as well as ATM networked workstations     

Reliability challenges of automotive power electronics

A high reliability of power electronic modules is an essential requirement for hybrid traction applications. This includes a high capability to withstand the stress of repeated active and passive thermal cycles in order to meet the lifetime requirements. Active power cycling requirements are not especially severe for hybrid traction applications compared to many industrial applications. The lifetime for passive thermal cycles by a change of ambient conditions in contrast is defined by the materials and the architecture of a power module. The classical module design with Cu base plates is limited in lifetime particularly with respect to passive temperature cycles due to CTE mismatch. The advanced pressure contact design eliminates the base plate together with the base plate solder and the terminal solder interconnections and thus enhances the thermal cycling capability. As a synergy effect, this design establishes a very balanced static and transient current distribution for paralleled chips. Finally, the last remaining solder interface – the chip solder layer – can be replaced by an Ag diffusion sinter technology. The presented cycling test results will confirm, that the first 100% solder-free module shows an improved performance in passive and active cycling tests.     

神经电生理微电极阵列检测系统研制

该文设计了基于微电极阵列的16通道神经电生理信号检测系统。检测系统由硬件和软件两部分组成,其中硬件部分可分为以下3个模块:微电极阵列接口模块,用于实现微电极阵列和检测系统的可靠连接;多通道信号放大模块,用于对微弱电生理信号进行提取并放大至合适的幅度;数据采集模块,对放大后的电生理信号进行高速数据采集并通过USB2.0接口和计算机相连。软件部分采用多线程、多缓存等技术保证对信号的实时观测和分析。对检测系统的主要参数进行了测试,并结合实验室自制神经微电极阵列对SD大鼠海马区脑切片进行神经电生理信号的检测。系统的输入噪声Vrms2 V,放大倍数为1000倍,频率带宽范围为10~3000 Hz,并且能够检测到放电幅度为20 V左右的神经电生理信号。该文针对微电极阵列神经电生理信号检测中的技术难点,从硬件和软件设计上保证微弱信号的提取,检测系统的分辨率可达0.6 V,各项参数能够满足神经电生理信号的检测需要。     

超宽带超低副瓣相控阵天线时域远场辐射特性研究

本文首先研究了天线时域辐射远场的基本原理,建立了计算公式.在此基础之上,分析了相控阵天线工作在窄脉冲条件下的时域辐射场,发现其时域方向性(如:时域远场峰值方向图、时域远场平均功率方向图)与频域方向性(频域远场方向图)并不一致,这种不一致性随着天线口径的增大或脉冲宽度的变窄而愈加明显,并且在天线注满时间之内表现得尤为突出.文章由此指出:对于超宽带超低副瓣相控阵天线来说,其性能用时域指标去衡量胜于用频域指标去衡量的新观点.     

Mode-Based Beamforming Arrays for Miniaturized Platforms

In this paper, a new and practical mode-based array concept is proposed. The key principle of this mode-based approach is the use of orthogonal radiation modes existing in highly coupled arrays as individual information channels so as to avoid mutual coupling and correlation. Consequently, mode-based arrays can be very compact in size but without suffering undesired effects such as impedance mismatch or pattern distortion. While providing a general theoretical discussion for this mode-based approach, a practical application example, namely, a compact electronically scanning array module is developed. With a suitable signal combining algorithm, the module is capable of forming and full 360^deg scanning of a high-gain radiation pattern in the azimuth plane. An experimental prototype has been fabricated on a traditional printed circuit board to validate the practicability of the proposed concept. Measurement results obtained are in good agreement with theoretical simulations, showing promising potential of mode-based array modules for modern miniaturized wireless devices.     

An architecture for electrically configurable gate arrays

An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead needed to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. This circuitry can also be used to test the device prior to programming and observe internal nodes after programming. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated     

一种低成本星载宽角扫描相控阵天线设计

设计了一种工作于X 频段的星载圆极化相控阵天线。相控阵天线单元的馈电探针与连接器进行了一体化设计,消除了焊点,提高了阵面的可靠性;同时阵列单元周围加载金属腔体结构,降低了单元间的耦合,展宽了天线波束,提高了阵列的扫描增益;阵面为全金属结构,可实现相控阵的均温性与内部热量的辐射,阵面自身具有较强的空间抗辐照能力,同时也能对相控阵内部的有源器件提供良好的辐照屏蔽。相控阵有源组件和合成网络采用瓦片架构,具有轻量化和低剖面的特点。所设计相控阵天线具有±60°宽角扫描能力和4%的工作带宽。