Principles of wet chemical processing in ULSI microfabrication

Fine patterning technology for integrated device manufacturing requires properties such as surface cleanliness, surface smoothness, complete uniformity, and complete etching linearity in wet chemical processing. An improved chemical composition for buffered hydrogen fluoride (BHF:NH₄F+HF+H₂O) is determined based on fundamental research into the chemical reaction mechanism of BHF and SiO ₂. Advanced wet chemical processing based on investigation of chemical reaction mechanisms and properties of liquid chemicals, concentrating on the SiO₂ patterning process by BHF, is described. The principles of wet chemical processing in silicon technology are based on the following: the determination of the dominant reaction (etching) species, the influence of the solubility of the etching products in BHF on etching uniformity and linearity, stability of chemical composition without solid-phase segregation, and an improvement of the wettability of liquid chemicals on the wafer surface by the addition of a surfactant     

Contact angle evaluation for laser cleaning efficiency

A laser cleaning technique using an excimer laser is introduced to remove the photoresist on a Si wafer surface and its cleaning characteristics have been investigated. To analyse the cleaning efficiency quantitatively, a scanning electronic microscope, energy dispersive spectroscope, surface scanner and contact angle measurement were employed. Among these methods, it was confirmed experimentally that the contact angle measurement could be applicable to analyse the laser cleaning efficiency effectively owing to its speed of measurement and low measurement cost.     

基于Al2O3中间层的InP/SOI晶片键合技术研究

研究了基于Al2O3中间层的InP/SOI晶片键合技术.该方案利用原子层沉积技术在SOI晶片表面形成Al2O3作为InP/SOI键合中间层,同时采用氧等离子体工艺对晶片表面进行活化处理.原子力显微镜和接触角测试结果表明,氧等离子体处理使得晶片的表面特性更适于实现键合.透射电子显微镜和X射线能谱仪测试结果证实,采用Al2O3中间层可以实现InP晶片与SOI晶片的可靠键合.     

Particle-free wafer cleaning and drying technology

It is reported that an NH₄OH-H₂O₂ solution is excellent for removing particulate contaminants from VLSI silicon wafers after chemical solution treatment. The ratio of NH₄ OH in the solution can be reduced down to 1/10 of the standard ratio while keeping high removal efficiency. By decreasing the NH₄ OH content, wafer damage which appears as a so-called haze during the NH₄OH-H₂O₂ treatment is reduced. To establish a particle-free wafer drying system, a particle-generation-free isopropanol (IPA) vapor drying system has been developed. By eliminating all possible particle generation sources from the drying system, ultraclean wafer drying equipment has been realized. A number of parameters to be controlled have been thoroughly investigated. Three were found to seriously influence surface cleanliness after drying: the water content in the IPA, temperature distribution around the wafers, and the IPA vapor velocity. The optimum drying conditions in which high quality of wafer surface cleanliness can be realized were confirmed experimentally     

PECVD oxide as intermediate film for wafer bonding: Impact of residual stress

The deposition rate, the etch rate in a HF-based solution and the residual internal stress of PECVD oxides are systematically analysed for various deposition conditions and post-anneal treatments. Rapid thermal anneal (RTA) at a temperature over 900 °C for 15 s is proven to be the most efficient to reduce the residual stress in the film and its etch rate in BHF solution, as well as to enhance its long term stability. The reduction of the internal stress in PECVD oxide is mandatory to minimize the wafer bow which degrades the wafer bonding quality. Bonded samples show that the resulting surface energy tends to vary inversely with the elastic energy stored by the conformation of the wafers during the direct bonding. About 45 μm wafer bow (3 inch wafer, 380 μm-thick) comes out as an upper bow limit, preventing direct bonding to occur. The use of a RTA step following the PECVD oxide layer deposition is demonstrated to be an efficient technological solution to minimize the wafer bow and thus maximize the bonding surface toughness. The experimental results presented in this paper highlight the importance of monitoring the residual stress in intermediate oxide layers to assure high quality and reliable bonding and thus future three-dimensional integration.     

WL-CSP reliability with various solder alloys and die thicknesses

WL-CSP is a low profile, true chip size package that is entirely built on a wafer using front-end and back-end processing. A new wafer level chip-scale package (WL-CSP) technology has been evaluated using a test vehicle, which has a 0.5 mm pitch of an 8 × 8 array of bumps on a 5 × 5 mm² die. The bump structure and package geometry have been optimized using simulation and validated by experimentation. The board used for reliability testing is a 1.2 mm thick, 2-layer FR-4 board with non-soldermask defined landpads with OSP (organic solderability preservative). The landpads are the same diameter as the 250 μm redistribution dielectric via size. Reliability data will be presented for three solder alloys and two wafer thicknesses. The first evaluation compares the reliability of solder alloys SnPbAg and two Pb-free alternatives: SnAgCu and SnCu. The second evaluation evaluates the potential reliability improvement of WL-CSPs by thinning the wafers. Standard thickness WL-CSP wafers are 27-mils. Wafers were thinned down to 4-mils thickness using two techniques. The first method is standard wafer backgrinding. The second is plasma etching, which results in a damage-free surface and improves wafer and die strength.     

Hybrid dry-wet chemical etching process for via holes for galliumarsenide MMIC manufacturing

Through the wafer via-hole connections for monolithic microwave integrated circuits (MMIC) manufacturing have been developed by combining reactive ion etching (RIE) and wet chemical spray etching processes for 100-μm-thick gallium arsenide wafers. The dry process is based on the use of SiCl₄-BCl₃-Cl₂ and BCl₃-Cl₂ gas mixtures at room temperature is a reactive ion etcher. The etching parameters are optimized for anisotropic etching, initially, followed by slightly isotropic etching. To remove the residual `lip' and surface roughness, following reactive ion etching, a dynamic wet chemical spray etching based on H₃PO₄-H₂O₂-H₂O at 45°C is used. The combined dry-wet etching approach is used to fabricate <120-μm diameter via-holes in 100-μm-thick GaAs substrates with a wider process latitude. With this process, the authors have achieved >95 percent yield across 3-in wafers. Metallized via-hole contacts to power FET chips show a contact resistance <20 mΩ per via for 5-μ-thick selective gold plating     

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H₂SO₄, 96%) and hydrogen peroxide (H₂O₂, 30%), 120 °C), SC1 (1:1:5 mixture of NH₄OH, H₂O₂ and H₂O, at 80 °C) or HF solution (6 parts of 40% NH₄F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film.     

Measurement and analysis of contact resistance in wafer probe testing

When testing IC chips using a wafer probe card, maintaining a low and stable contact resistance is essential. However, the electrical contact between the probe and the bonding pad of the IC chip becomes unstable following repeated probing operations since particles from the chip surface gradually accumulate on the probe tip. The contamination caused by these particles causes the contact resistance to increase. Accordingly, this study develops an experimental procedure for investigating the effect of the particle contamination on the magnitude and stability of the contact resistance. Initially, an experiment is performed to establish the contact resistance between a clean tungsten probe and various specimen surfaces, i.e. aluminum, gold and copper, at various levels of overdrive. Subsequently, an experiment is conducted to investigate the accumulation of surface particles on the probe tip following multiple contacts of the probe with the wafer surface. The extent of particle contamination following 10,000, 30,000 and 50,000 contacts, respectively, is examined using a scanning electron microscope (SEM). The contact resistance of the contaminated probes is then measured at various levels of overdrive. The experimental results are then integrated to establish a suitable tradeoff between the contact resistance, the overdrive displacement, and the number of contacts.The results from the contact resistance experiment conducted using a clean tungsten probe indicate that the surface specimens with a lower resistively generate a lower contact resistance. For example, the contact resistance between the tungsten probe and the copper foil is approximately 100 mΩ, and becomes stable at an overdrive of 45 μm. However, the contact resistance increases with an increasing number of contacts. In general, the probe should be removed for cleaning following 30,000 contacts to ensure that a contact resistance of less than 1 Ω is maintained.     

Adhesion of NCF to oxidized Si wafers after oxygen plasma treatment

The effect of oxygen plasma treatment on the adhesion between nonconductive film (NCF) and oxidized Si was investigated. Oxidized Si wafers were treated with oxygen plasma for 5 min and then rinsed in de-ionized water (DIW). The water contact angle was measured by means of the sessile drop technique and the surface roughness was measured by means of atomic force microscopy. The adhesion of the NCF to the oxidized Si wafer was evaluated by means of a single-lap shear test after bonding at 150°C for 5 s. Oxygen plasma treatment decreased the water contact angle. The roughness of the oxidized Si wafer decreased when oxygen plasma treatment was applied alone, but was increased when both oxygen plasma treatment and DIW rinse were applied. Similarly, the shear strength decreased when oxygen plasma treatment was applied alone, but the adhesion of NCF increased when both oxygen plasma treatment and DIW rinse were applied. The increased surface roughness of the oxidized Si wafer played an important role in increasing the adhesion between the NCF and the oxidized Si wafer. The shear strength further increased after post-heat treatment at 170°C for 1 hr or at 280°C for 15 s. Low shear strength observed before post-heat treatment was ascribed to incomplete NCF curing. Differences observed in the adhesion strength between two types of NCF were attributed to differences in their curing degrees and their degrees of surface coverage of the oxidized Si substrates.     

Effect of surface preparation on Ni Ohmic contact to 3C-SiC

The effect of roughness and chemical treatment of 3C-SiC film surface on Ni ohmic contact was studied in this work. 3C-SiC(1 1 1) film was grown on Si(1 1 1) in a chemical vapor deposition reactor. The 3C-SiC surface was polished using a chemical mechanical polishing (CMP) technique to get a smooth and flat surface. The polished surface was oxidized and then was etched in BHF solution to remove subsurface damages formed during the CMP process. The morphology of thus prepared silicon carbide (SiC) surfaces was investigated using SEM and AFM. Ni contact resistance to the 3C-SiC films was evaluated using linear transmission line method pattern. The formation of good ohmic contact characteristics was observed from Ni contact to all the tested SiC samples. After the CMP process, it was found that the RMS roughness of 3C-SiC surface apparently reduces and the specific contact resistance to 3C-SiC decreases as well, in proportion to the SiC surface roughness. The sacrificial oxidation and etching of the polished SiC surface abruptly decrease the contact resistance to be 3.7×10⁻⁴ Ω cm². It was shown that the surface morphology and subsurface damage concentration of 3C-SiC films are important factors to give a great effect on the contact characteristic of the 3C-SiC films. However, it was considered that the reduction of subsurface damage concentration is essential to get better contact resistance to 3C-SiC surface.     

Development of three-dimensional memory die stack packages usingpolymer insulated sidewall technique

A newly designed three dimensional (3-D) memory die stack package has been established, and the prototype of the 3-D package using mechanical dies has been successfully demonstrated. Fabrication processes of the 3-D package consist of: (1) wafer cutting into die segments; (2) die passivation including sidewall insulation; (3) via opening on the original I/O pads; (4) I/O redistribution from center pads to sidewall; (5) bare die stacking using polymer adhesive; (6) sidewall interconnection; and (7) solder balls attachment. There are several significant improvements in this new 3-D package design compared with the current 3-D package concept. The unique feature of this newly developed package is the sidewall insulation of dies prior to the I/O redistribution of dies, which produces (1) better chip-to-wafer yields and (2) significant process simplification during subsequent fabrication steps. According to this design, 100% of die yields on a conventional wafer design can be obtained without any neighboring die losses which usually occur during the I/O redistribution processes of conventional 3-D package design. Furthermore, the new 3-D package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. It is proven that the mechanical integrity of the prototype 3-D stacked package meets requirements of the JEDEC Level III and 85°C/85% test     

用单片清洗设备进行晶圆背面清洗(英文)

晶圆背面的污染降低了半导体器件的成品率,而当器件进入100nm技术节点之后成品率的降低便显得尤为重要。因此,目前众多的器件制造厂家就要求在进行片子正面清洗的同时对其背面也能够实现清洗。由Akrion公司制造的Mach2HP系统就是这样一种单片清洗设备,它具有清洗晶圆正反两面的功能。在起初评价时,设备经过了大量的粒子去除效率的变化。这种大量的变化使我们不能了解这种设备真实的清洗能力。氮化硅(Si3N4)粒子污染的晶片被用以进行粒子去除效率测试。我们发现有Si3N4粒子的晶片引起了背面粒子去除效率的变化。这种含Si3N4粒子的晶片是通过在裸芯片上沉积Si3N4粒子而特意准备的。我们发现,一些较大的Si3N4粒子在晶片清洗时又分解成更小的粒子。如若在清洗之后分解的粒子仍保留在晶片上,它们便会降低晶片总的粒子去除效果。因此,在这些粒子沉积到晶片上之前,这些粒子群需要进一步分解成实际的粒子。经过了解晶片的预习处理,我们实现了这种清洗设备背面清洗效果的评价。     

Plasma etching of polysilicon and Si3N4in SF6with some impact on MOS device characteristics

Accurate delineation of the circuit materials polycrystalline silicon ("poly"), and silicon nitride are important requirements of most SFC process sequences. We have investigated the use of SF6as an active species in the parallel-plate plasma etching of these materials. For the etching of poly there is good selectivity (better the 50:1) with respect to the etch rates of SiO2and positive photoresist. This process has been used in the fabrication of MOS transistor with 3-µm poly-gate lengths and threshold voltages vary by less than 0.05 V both across a wafer and from wafer to wafer. Etching of nitride is less selective and less isotropic than that of poly.     

A thin transition film formed by plasma exposure contributes to the germaniumsurface hydrophilicity

Plasma treatment and 10% NH₄OH solution rinsing were performed on a germanium (Ge) surface. It was found that the Ge surface hydrophilicity after O₂ and Ar plasma exposure was stronger than that of samples subjected to N₂ plasma exposure. This is because the thin GeO_x film formed on Ge by O₂ or Ar plasma is more hydrophilic than GeO_xN_y formed by N₂ plasma treatment. A flat (RMS<0.5 nm) Ge surface with high hydrophilicity (contact angle smaller than 3°) was achieved by O₂ plasma treatment, showing its promising application in Ge low-temperature direct wafer bonding.     

The technological requirements for power by fusion

The major technological requirements for fusion power, as implied by current conceptual designs of fusion power plants, are elucidated and assessed. As the point of departure, the four fusion reactor concepts which have been most thoroughly considered in these design studies are described; they are the mirror, the theta-pinch, the tokamak, and the laser-pellet concepts. The required technology is discussed relative to three principal areas of concern: 1) the power balance, that is, the unique power-handling requirements associated with the production of electrical power by fusion; 2) reactor design, focusing primarly on the requirements imposed by a tritium-based fuel cycle, thermal-hydraulic considerations, and magnet systems; and 3) materials considerations, including surface erosion, radiation effects, materials compatibility, and neutron-induced activation. The major conclusions are summarized in a final section where it is noted that research and development programs have been initiated to satisfy the technological requirements associated with the realization of commercial fusion power.     

InSb晶片化学抛光研究

机械抛光会给InSb晶片表面造成一定程度的机械损伤,增加表面的粗糙度,从而影响器件的性能.化学抛光可以有效地去除表面划痕,改善晶片的表面形貌,降低粗糙度.用低浓度的澳一甲醇溶液对机械抛光后的InSb晶片进行了化学抛光,并对化学抛光前后的InSb晶片进行了表面形貌、总厚度偏差(TTV),粗糙度、表面组分和杂质对比分析.实验结果表明,用低浓度的溴-甲醇溶液对InSb晶片进行化学抛光,腐蚀速率平稳且容易控制,能有效去除表面划痕,从而得到光滑、平坦的表面.晶片表面的粗糙度为6.443nm,TTV为3.4μm,In/Sb原子比接近1.与传统的腐蚀液CP4-A,CP4-B相比,用低浓度的溴-甲醇溶液对InSb晶片进行化学抛光,可以获得更低的表面粗糙度和TTV,且In/Sb的原子比更接近于1.     

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical–mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8–5.2 $Omega $ have been obtained from via chain test structures and an average specific contact resistivity of 1.7$,times ,$10$^{-8} Omega {hbox{cm}}^{2}$ , measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.      

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.     

Current Status and Future of Intelligent Industrial Robots

This paper reviews the current status of industrial robots and discusses their future from the viewpoint of the basic key functions which will be required for future intelligent applications. Ten basic key functions are introduced as examples which satisfy the following four conditions: 1) low price, 2) high performance, 3) high reliability, and 4) simplicity. All of these functions are necessary if robots are to perform tasks more effectively in actual applications. The effectiveness of the functions are explained using ten industrial robots or robotic machines which have been developed by Hitachi.