共查询到16条相似文献,搜索用时 78 毫秒
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全加器是算术运算的基本单元,提高一位全加器的性能是提高运算器性能的重要途径之一。首先提出多数决定逻辑非门的概念和电路设计,然后提出一种基于多数决定逻辑非门的全加器电路设计。该全加器仅由输入电容和CMOS反向器组成,较少的管子、工作于极低电源电压、短路电流的消除是该全加器的三个主要特征。对这种新的全加器,用PSpice进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。 相似文献
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全加器是算术运算的基本单元,设计结构简单的全加器有利于缩小数字自理芯片的面积。根据最新的XOR门结构设计了一种新的全加器,这种结构的一位全加器只用20只MOS管,对这种新的全加器,用PSPICE进行了晶体管级模拟。结果显示,这种新的全加器能正确完成加法器的逻辑功能。 相似文献
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量子全加器构造的探讨 总被引:1,自引:0,他引:1
本文探讨了由Toffoli门和受控非门等量子逻辑门构成低位输入、低位输出的量子全加器的电路,并分析了该种量子全加器的变换操作。通过比较推导出有多位输入、多位输出量子全加器的电路组合规律. 相似文献
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单双稳态转换逻辑单元(MOBILE)是基于共振隧穿二极管(RTD)电路的一个重要逻辑单元,非常适合阈值逻辑电路设计。由MOBILE可以构成阈值逻辑门(TG)和广义阈值逻辑门(GTG)等阈值逻辑电路。本文通过将三变量异或函数转化为较简单、理想的GTG输入输出函数形式,设计了由GTG构成的新型三变量异或门,并利用该三变量异或门设计了新型的全加器。通过HSPICE仿真和性能比较,该全加器不仅器件数量少,输出延时短,而且能达到较高的工作频率、更小的电路功耗与功耗-延迟积。 相似文献
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为提高新一代纳米器件量子元胞自动机(QCA)电路的稳定性及可靠性,提出了一种容错1位全加器,然后通过QCADesigner软件来仿真分析1位容错全加器,验证了该设计的可行性及它具有较好的容错性,该设计对复杂QCA电路的容错性的研究起到借鉴作用. 相似文献
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一种基于互补型单电子晶体管的全加器电路设计 总被引:4,自引:0,他引:4
基于单电子晶体管(SET)的I-V特性和CMOS数字电路的设计思想,提出了一种由28个互补型SKT构成的全加器电路结构。该全加器优点为:简化了“P—SET”逻辑块;通过选取一组参数使输入和输出高低电平都接近于0.02mV和0mV,电压兼容性好;延迟时间短,仅为0.24ns。SPICE宏模型仿真结果验证了它的正确性。 相似文献
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The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts. 相似文献
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量子全加器是量子计算机的基本单元,为了减少能耗,降低构造成本及物理实现难度,本文提出一种新型n位量子全加器,使用3n个CNOT(Controlled NOT)门和2n-1个Toffoli门实现n位量子加减法,采用超前进位方式,不含进位输入,通过最高溢出标志位判断加法的进位和减法的正负号,标志位不参与高低位计算,不增加电路延时,适合n位量子并行计算.随机生成4、8、16和32位数分别进行加减仿真操作,验证了全加器的正确性.该全加器量子代价较低,结构简单,有利于提高集成电路规模和集成度. 相似文献
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Lin J.-F. Hwang Y.-T. Sheu M.-H. Ho C.-C. 《IEEE transactions on circuits and systems. I, Regular papers》2007,54(5):1050-1059
In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases 相似文献
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一种基于新型Precharge PFD的CMOS CPPLL设计 总被引:2,自引:0,他引:2
文章描述了一种基于新型无"过充"的边沿触发的鉴频鉴相器的CMOS电荷泵锁相环设计与仿真.电路设计基于UMC 2.5V 0.25μm CMOS工艺.Spice仿真结果显示,它可以实现快速锁定和较低的抖动性能. 相似文献
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《微纳电子技术》2019,(11)
将一种电压阈值型压控双极性忆阻器模型与CMOS反相器进行混合设计,实现了"与"、"或"、"与非"、"或非"基本逻辑门。通过构建"异或"逻辑门新结构,提出一种基于混合忆阻器-CMOS逻辑的全加器电路优化设计方案。最后,分析忆阻器参数β,V_t,R_(on)和R_(off)对电路运算速度和输出信号衰减幅度的影响,研究了该优化设计的电路功能和特性,经验证模拟仿真结果与理论分析结果具有较好的一致性。研究结果表明:全加器优化设计结构更简单,版图面积更小,所需忆阻器数量减少22.2%,CMOS反相器数量减少50%;增大参数β值可提高运算速度,增大忆阻值比率R_(off)/R_(on)可减小逻辑输出信号衰减度。 相似文献