Java并行注释规范JAC的扩展

JAC是基于扩展Java注释描述其并行编程的技术,具有隐藏线程、同步等并行编程机制,把应用逻辑与并行逻辑分离等优点.为了克服目前版本的JAC规范在执行类静态方法对象间的并行时可能会造成类静态变量的不确定性的缺点,扩展了JAC规范,用exclusive并行注释来控制Java对象间的方法的并行性,同时改进JAC预编译器,为程序中每个类维护一张ID列表,使JAC预编译器支持类静态方法对象间的并行编程.从而提高了JAC技术解决复杂的并行编程问题的能力.     

信息时代的精灵——Java语言讲座(六)——Java应用程序制作与Java高级技术

一、Java中的多线程 在前面的讲座(三)中,我们曾介绍了线程的基本概念以及利用线程技术进行简单程序设计的方法和实例。在这一讲中,我们介绍Java高级编程技术中的多线程技术。 每个线程都是一个线程组中的成员,线程组把多个线程集成为一个对象,通过线程组可以同时对其中的多个线程进行操作,如启动或暂停一个线程组中的所有线程等。Java的线程组由包java.lang中的类ThreadGroup实现。 1.线程和线程组 在生成线程时,可以指定将线程放在某个线程组中,也可以由系统将它放在某个缺省的线程组中。通常缺省的线程组就是生成该线程时所在的线程组。但是一旦线程加入了某个线程组,它将一直是这个线程组的成员,而不能被移出这个线程组。     

基于Java的网络编程及多线程同步机制

介绍Java的网络编程基础，说明了线程的几个状态间的相互转换，对Java的多线程的同步机制和线程间通信机制作了分析，并结合创建一个远程文件服务器的实例，来探讨Java的网络编程对多线程同步机制的支持。     

基于内存模型的Java并发编程

多核处理器为并发编程打开了一扇扇新的大门，Java内置的多线程机制可以方便地实现多个并发程序的开发以及多任务同时执行，但是Java线程之间的通信对程序员完全透明，内存可见性问题很容易困扰Java开发人员，本文将简单分析基于内存模型的Java并发编程。     

JAVA线程机制在FTP客户端程序中的应用

为使程序具有更好的交互性，通常采用多线程机制。Java程序设计语言将线程支持与语言运行环境结合在一起，使多线程应用程序的开发变得更加容易。本重点讲述了Java的线程机制在FTP客户端程序中的应用。     

操作系统中的进程、线程与Java的多线程

本文从进程、线程、多线程的基本概念和属性出发,对进程与线程、Java与多线程的关系进行详细地论述,并对Thread类在Java程序中的应用、线程的创建和运行等提出示例。     

线程池在网络服务器程序中的应用

线程池技术在现代网络服务器应用程序中，尤其是在Web应用程序中被大量应用。详细地探讨了线程池技术的工作原理，实现方法以及利用线程池后给服务器应用程序带来的益处。利用Java语言编写了一个线程池类。     

Java程序的多线程机制

多线程是Java的一个重要特点,这使得在一个Java程序内部可同时进行多种运算,从而充分利用系统资源,提高程序运行效率,本文结合开发中的实例论述在Java程序中创建线程和实现线程体的机制。     

长持续时间数据流的并行检测算法

针对现有长持续时间数据流检测算法的实时性差、检测精度与估计精度低的问题,提出长持续时间数据流的并行检测算法。基于共享数据结构的长持续时间数据流的并行检测算法中不同线程访问共享数据结构,线程之间的同步开销过大。在此基础上,基于独立数据结构的长持续时间数据流的并行检测算法中不同线程具有本地数据结构,线程之间不需要同步,产生较少的开销。理论分析与实验结果表明,基于独立数据结构的长持续时间数据流的并行检测算法具有良好的时间效率、较高的检测精度和流持续时间估计精度。     

JAVA线程机制在FTP客户端程序中的应用

为使程序具有更好的交互性,通常采用多线程机制。Java程序设计语言将线程支持与语言运行环境结合在一起,使多线程应用程序的开发变得更加容易。本文重点讲述了Java的线程机制在FTP客户端程序中的应用。     

基于并发事务逻辑的Web服务编制验证

 服务编制解决的是组织之间的业务集成问题,面临的是一个广泛分布、动态、自治、异构的网络环境,保障组合服务的正确执行以及相关特性的验证问题显得尤为重要.形式化方法是一种有效的解决方法,服务编制需要建立在严格的形式化模型的基础上,可以通过具有明确的、形式化语义的形式化模型研制验证工具来完成组合服务正确性的验证.本文基于并发事务逻辑(CTR:Concurrent TRansaction Logic)对服务编制的元素进行了描述和建模,给出了从WS-BPEL到并发事务逻辑的转换规则,讨论了服务编制在CTR中的验证问题以及WS-BPEL和CTR的表达能力,最后给出了一个实际的服务编制在CTR中建模的例子,验证了服务编制的CTR模型的有效性.     

一种基于区间时序逻辑模型检测的入侵检测算法

Model checking based on linear temporal logic reduces the false negative rate of misuse detection. However, linear temporal logic formulae cannot be used to describe concurrent attacks and piecewise attacks. So there is still a high rate of false negatives in detecting these complex attack patterns. To solve this problem, we use interval temporal logic formulae to describe concurrent attacks and piecewise attacks. On this basis, we formalize a novel algorithm for intrusion detection based on model checking interval temporal logic. Compared with the method based on model checking linear temporal logic, the new algorithm can find unknown succinct attacks. The simulation results show that the new method can effectively reduce the false negative rate of concurrent attacks and piecewise attacks.     

Design for concurrent error detection and testability instorage/logic arrays

Storage/Logic Arrays (SLA's) represent a structured logic array approach to the design of VLSI sequential logic. Design for concurrent error detection and testability is complicated in these arrays by the presence of embedded memory elements and multiple levels of logic. A means of designing SLA's for ease of testability and concurrent error detection (CED) is provided in this paper. Test sets for static and dynamic CMOS circuits are described. Fault and error coverage is presented and performance and area costs are analyzed for example circuits. In addition, a means of implementing dynamic CMOS SLA's is presented and shown superior to previous NMOS, static CMOS, and dynamic CMOS approaches based upon power consumption and simplicity of design     

A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.     

Concurrent error detection in highly structured logic arrays

Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.     

LS SIMD微处理器中的三组指令并发执行的设计

文章介绍了LS SIMD微处理器中实现三组指令并发执行的可能性和必要性，分析了三组指令并发执行给流水线带来的影响，并讨论了控制逻辑对三级指令并发执行的控制及其实现形式。     

A formal logic of plans in temporally rich domains

This paper outlines a temporal logic extended with two modalities that can be used to support planning in temporally rich domains. In particular, the logic can represent planning environments that have assertions about future possibilities in addition to the present state, and plans that contain concurrent actions. The logic is particularly expressive in the ways that concurrent actions can interact with each other and allows situations where either one of the actions can be executed, but both cannot, as well as situations where neither action can be executed alone, but they can be done together. Two modalities are introduced and given a formal semantics: INEV expresses simple temporal possibility, and IFTRIED expresses counteffactual-like statements about actions.     

Modular and rapid testing of SOCs with unwrapped logic blocks

Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly by adapting the TestRail architecture, which uses only the test control mechanism and the test instructions available through the IEEE 1500 standard for embedded core test. A new test scheduling algorithm, which facilitates a concurrent test of both unwrapped logic blocks and IEEE 1500-wrapped cores, is proposed, and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small.     

RSYN: a system for automated synthesis of reliable multilevelcircuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN     

Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (from the point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs.