具有DSP功能的16位微控制器80296SA

８０２６９ＳＡ是ＩＮＴＥＬ公司推出的带有ＤＳＰ功能的１６位微控制器，很适合于应用在需要进行数字信号处理的场合。文中介绍了８０２６９ＳＡ的特性以及它特有的ＤＳＰ功能。并给出８０２６９ＳＡ在有关测控系统的ＣＰＵ板上的应用实例。     

IS-95码分多址系统上行信道接收机捕获单元的设计及FPGA实现

捕获是扩频通信系统的关键技术之一，本文针对ＩＳ－９５码分多址蜂窝通信系统标准，给出了一种适合于上行信道接收机的捕获方案，分析了虚警概率和检测概率，并介绍了该方案的ＦＰ－ＧＡ实现。该方案简单可行，采用并行结构，具有捕获时间短，硬件资源消耗少的特点。     

分布式传感器数据融合中的双门限航迹相关算法

本文提出了两种适合于分布式多传感器数据融合的双门限入迹相关算法。本文对这两种双门限航迹相关准则进行了详细的描述，研究了航迹相关质量设计、多义性处理和漏相关概率的伏计方法，并通过仿真将它们与两个经典方法进行了比较。仿真结果表明，在密集目标环境下和／或交叉、分岔和机动航迹较多的场合，双门限航迹相关算法的性能明显优于传统方法，其正确相关率比传统方法提高了３５％。     

模糊控制器专用集成电路的设计与实现

提出了一种用数字逻辑电路设计模糊控制器的方法。该模糊控制器电路不用ＣＰＵ，全部算法由数字逻辑电路实现，具有运算速度快的特点，适合于需要高速控制的场合。该模糊控制器电路具有被激活的规则自动生成功能，不需要大规模的ＲＡＭ或ＲＯＭ存储模糊规则，电路规模小，易于实现，特别适合于输出控制量为离散值的应用场合。已在一片ＦＰＧＡＸｉｌｉｎｘ４０１０ＰＧ１９１－６上实现了该模糊控制器电路，并成功地应用于温控系统。     

雷达对抗混合策略求解的神经网络方法

本文把神经网络方法用于雷达对抗研究，提出了求解雷达对抗混合策略的神经网络方法，仿真结果表明了方法特别适合于雷达模糊对抗的场合。     

SCPC／DAMA卫星通信系统中的信道强拆方案探讨

本文提出了ＳＣＰＣ／ＤＡＭＡ卫星通信系统中三种信道强拆的方案，并分析了其特点和应用场合。     

SRS声音恢复系统初探

本文通过对ＳＲＳ原理的分析及主观和客观评价，阐明了ＳＲＳ的工作机理和要点，并且根据其在应用中的实际效果给出适合它的运用场合。     

BiCMOS结构中阱特性的研究

叙述了以双极型工艺为主体的ＢｉＣＭＯＳ结构中ｐ阱电阻比值非线性的特性及其与芯片合格率的关系。在ｐ阱下面采用埋层，抑制或消除了ＢｉＣＯＭＳ中；ｐ阱结构的寄生效应，从而提高了芯片合格率。     

B－ISDN与现有网络互连的研究

本文主要围绕Ｂ－ＩＳＤＮ与现有各种网络（如ＰＳＰＤＮ、ＰＳＴＮ、ＬＡＮ等）的互连问题展开讨论，并针对不同的应用场合提出了相应的互连解决方案。     

ISDN用户网络接口专用集成电路

本文较为系统、全面地介绍了近年来一些国际著名的通信设备及集成电路产家所推出的各种ＩＳＤＮ专用ＶＬＳＩ芯片，包括基本速率Ｓ／Ｔ接口，话音处理、分组处理及速率适配等电路。重点分析、比较了它们的设计思想和特点，并由此指出了它们各自的应用场合。     

多目标多约束的集成电路统计优化策略

对于集成电路设计、生产过程中的多目标、多约束统计优化问题,本文提出了“合格率足够高”的优化宗旨,并从概率论的基本原理出发,结合集成电路的特点,导出了一种合格率的近似表述方法,提出的变权重Monte Carlo法编程简便,效率高。采用这些优化策略设计的集成电路合格率优化系统取得了比较好的结果。     

Multidisciplinary heat generating logic block placement optimization using genetic algorithm

A multidisciplinary optimization methodology for placement of heat generating semiconductor logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using a genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to determine the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multidisciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. Capabilities of the present methodology are demonstrated by applying it to several standard benchmarks. The multidisciplinary logic block placement optimization results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared to the case in which only the wiring length is minimized.     

深亚微米SRAM电流感应电路的分析和优化*

本文对随机掺杂浮动效应下传统的电流感应电路的可靠性做了定量的分析。主要考虑了晶体管尺寸、控制信号的下降时间和特定晶体管的阈值电压三方面对电流感应电路可靠性的影响。在这个基础上,我们做了最终的优化来提高电流灵敏放大器的可靠性。在90纳米工艺下,仿真结果显示最终优化后的电流感应电路的失败率能够比优化前减少百分之八十,而延时只是稍微增加一点。     

基于NOMA的D2D辅助中继系统性能分析与优化

本文针对两阶段NOMA(Non-Orthogonal Multiple Access)-D2D((Device-to-Device)辅助中继场景提出了一种功率优化算法，推导分析了各用户的中断概率。构建了以最大化系统各态历经容量为目标的优化问题，由于一、二两阶段通信用户的差异性，重点优化了对提升系统容量起决定作用的第一阶段功率分配因子，分析证明了原优化问题存在极值点，并利用凸函数性质获得了优化的功率分配因子，并且进一步推导分析了各个用户的中断概率。仿真结果表明，理论推导的中断概率值与仿真结果完全一致，证明了推导的正确性，本文提出的功率优化算法能显著提高系统容量，且降低了中断概率。例如当SNR为35dB时，本文算法可以提高约17.6%的系统容量，而作为辅助中继用户的中断概率大约降低了81.3%。      

基于IC产品分档的成品率与效益协调优化设计方法

文章在对IC产品按性能优劣分档的基础上，构造了一个既能体现IC产品的性能优劣和价格大小，又可根据各档次IC产品的市场价格进行调节的性能价格函数：Ep(X)=-1pln{e^-p ∑Mi=1e^P(kiΦi(x)-α)}，从而建立了成品率与效益协调优化模型：maxX^0YE(X^0)=∫R^aEp(X)P(X,X^0)dX。     

Performance and Optimization of Switched Diversity Systems for the Detection of Signals with Rayleigh Fading

The performance and optimization of switched diversity systems are considered. First, the one-dimensional distribution and probability density functions of the envelope of the received signal are obtained for three different switching strategies. This information is used to obtain the average probability of bit error for the case of non-coherent detection of binary FSK signals with Rayleigh fading envelopes and additive white Gaussian noise. The optimization of two of these switching strategies is then considered, and it is shown that by proper selection of switching thresholds, the average probability of bit error during detection can be minimized. It is also shown that these optimized switching strategies yield a significant improvement in performance over non-diversity systems and can approach the performance of more complex receivers such as maximal ratio combining. Computer simulations of switched diversity systems using a practical field model are used to verify the analysis.     

A numerical integration-based yield estimation method for integrated circuits

A novel integration-based yield estimation method is developed for yield optimization of integrated circuits.This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal,the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation(BCT).In order to reduce the estimation variances of the model parameters of the density function,orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations.The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed.Two yield estimation examples,a fourth-order OTA-C filter and a three-dimensional(3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values.Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases.Therefore,our method is more suitable for parametric yield optimization.     

集成电路参数中心值和容差的耦合设计方法

基于对集成电路参数成品率中心值设计和容差分配的研究,该文提出了一种参数成品率中心值设计和容差分配耦合求解最优设计值的算法。该算法不需要设计者对电路或工艺的物理结构非常熟悉,从任意初始设计值和任意大小的容差,算法均可收敛到可接受域中的最优设计值。另外,根据工艺线的容差,算法可确定集成电路的最优参数成品率,也可根据实际要求选择适当容差的工艺线,以降低生产成本、提高效益。最后用实例证明了该算法的可行性和实用性,得到了满意的结果。     

Analysis and optimization of current sensing circuit for deep sub-micron SRAM

A quantitative yield analysis of a traditional current sensing circuit considering the random dopant fluctuation effect is presented.It investigates the impact of transistor size,falling time of control signal CS and threshold voltage of critical transistors on failure probability of current sensing circuit.On this basis,we present a final optimization to improve the reliability of current sense amplifier.Under 90 nm process,simulation shows that failure probability of current sensing circuit can be reduced by 80%after optimization compared with the normal situation and the delay time only increases marginally.     

一种基于数值积分的集成电路成品率估计方法

本文提出了一种基于数值积分的集成电路成品率估计方法。该方法通过直接在可接受域上对性能的联合概率密度函数进行积分获得成品率的估计。为达到此目的,性能的仿真数据须先经由Box-Cox变换 (BCT) 转化为服从多变量正态分布的数据。同时,文中采用了基于正交表的改进拉丁超立方体抽样法 (OA-MLHS) 对电路的工艺扰动参数实施抽样,如此可以大幅减小联合概率密度函数中分布参数的估计方差。文中对结合使用OA-MLHS与BCT从而减少了分布参数的估计方差的数学原理进行了分析。以一个四阶OTA-C低通滤波器和一个三维二次函数的成品率估计为例,在不同的样本量及成品率水平的组合下,对包含拉丁超立方体抽样和重要抽样等的六种不同的成品率估计法做了性能比较。大量的仿真证明本文所述的方法无论在精度还是效率上都要优于其他几种方法。因此,该方法更加适用于集成电路的成品率优化。