Zero-input limit cycles and stability in second-order fixed-point digital filters with two magnitude truncation quantizers

This paper is concerned with the stability analysis of second-order direct-form digital filters with two magnitude truncation quantizers. Zero-input stability is proved for the parameter regions where no conclusion can be drawn using the methods previously suggested in the literature. The areas of the parameter plane in which only limit cycles of period 1 or 2 exist, are determined and related to the cycle amplitudes. Finally, a transition graph is suggested to study the convergence patterns of the filter output.     

Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures

Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed finite-length impulse response (FIR) filter structures. In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required. The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90 nm CMOS process.     

Design of f.i.r. direct-form digital filters with two quantisation steps

The direct-form realisation of f.i.r. linear-phase digital filters is investigated when the coefficients are separated in two groups with different quantisation steps. It is shown in an example that considerable improvement in coefficient word length can be achieved by this technique.     

Complex digital oscillators and FSK modulators

The authors present complex-valued free running oscillators derived from digital filter structures. Four alternative approaches of complex direct-form and coupled-form oscillator structures are discussed leading to a multiple-output direct-form oscillator as the best solution from the viewpoint of computational efficiency. Two inherent advantages of direct-form structures can be avoided by appropriate means. The problem of poor frequency resolution at low frequencies is solved by a method called two's complement improvement (TCI). An oscillator frequency displacement is discovered which is caused by correlation between one state variable and the quantization error using finite arithmetic. This frequency error can be substantially reduced by appropriate error noise shaping. Some telecommunication applications like fixed-frequency complex oscillators for baseband signal processing, complex baseband frequency shift keying (FSK) modulators, and multiple-phase oscillators for multipath filters are discussed     

Efficient computation of time-varying and adaptive filters

Two techniques for efficient computation of filters that support time-varying coefficients are developed. These methods are forms of distributed arithmetic that encode the data, rather than the filter coefficients. The first approach efficiently computes scalar-vector products, with which a digital filter is easily implemented in a transpose-form structure. This method, based on digital coding, supports time-varying coefficients with no additional overhead. Alternatively, distributed-arithmetic schemes that encode the data stream in sliding blocks support efficient direct-form filter computation with time-varying coefficients. A combination of both of these techniques greatly reduces the computation required to implement LMS adaptive filters     

On limit cycles inn-order direct-form digital filters

The relationship between the elements in the vector of any limit cycle due to rounding in ann-order direct-form digital filter is established. Some bounds on the elements in such vectors are also determined. Sufficient conditions for the accessibility of period-r limit cycles due to rounding inn-order digital filters are presented.     

Sufficient stability bounds for slowly varying direct-formrecursive linear filters and their applications in adaptive IIR filters

This article derives a sufficient time-varying bound on the maximum variation of the coefficients of an exponentially stable time-varying direct-form homogeneous linear recursive filter. The stability bound is less conservative than all previously derived bounds for time-varying IIR systems. The bound is then applied to control the step size of output-error adaptive IIR filters to achieve bounded-input bounded-output (BIBO) stability of the adaptive filter. Experimental results that demonstrate the good stability characteristics of the resulting algorithms are included. This article also contains comparisons with other competing output-error adaptive IIR filters. The results indicate that the stabilized method possesses better convergence behavior than other competing techniques     

A separation theorem for finite-precision digital systems

For models of zero-input direct-form digital filters implemented in fixed-point digital hardware it is known that if saturation arithmetic is used and stability holds when the quantization is ignored, then the amplitude of all limit cycles can be made arbitrarily small by making the bound on the magnitude of the quantization sufficiently small. In that sense the effects of quantization and overflow can be considered separately. Recently, this proposition was extended to the case in which the input need not be zero. Here we give a result to the effect that quantization and overflow can be considered separately for a much more general class of discrete-time systems, and we give as an example an application of this result to systems governed by state equations.     

Design of FIR digital filters using prescribed subfilters

A method for the design of linear-phase digital filters by the tapped cascaded interconnection of identical subfilters is presented. The method is an extension of the method proposed by Saramaki (1987). An example is given to show that the number of distinct multipliers of the filter determined by the proposed method is less than that of filters determined by Saramaki's method (1987). We also consider the case in which the subfilters are determined by multiple use of a single filter. In particular, if we can make the subfilters multiplierless then the number or multiplications per sample required to implement the overall filter is less than that required by the direct-form minimax method. Methods for the design of computationally efficient filters are also developed based on the proposed transformation method. The multiplication rate of the overall filter is the same as that of the prototype filter. It is very low as compared to that designed by the equivalent direct-form minimax method. With the proposed transformation method, methods for the design of a filter having nth-order tangency at both ends (0, π) are also developed. This is an extension of Vaidynathan's method (1985) and the proposed transformation method. The advantages of the method are that the resulting filters have very flat passbands and the stopbands are computationally efficient.     

Transposed FIR filter structure with time-varying coefficients fordigital data resampling

A new time-domain derivation is presented for interpolation and decimation by a fractional factor U/D. Though it is well known that such a filter can be implemented using a direct-form I, FIR filter with time-varying coefficients, a novel time-varying alternative, using a transposed filter structure, is described. Time-varying filters are especially important for implementation on a digital signal processor. The new time-varying structure has the advantage of reduced buffer memory for downscaling, or increased parallelism for high-speed upscaling, compared to the conventional time-varying structure     

VLSI architectures for high-speed and flexible two-dimensionaldigital filters

Flexible VLSI architectures for high-speed 2-D finite-impulse-response (FIR) and infinite-impulse-response (IIR) digital filters are described. Cyclical parallel processing structures for 2-D FIR and IIR digital filtering are derived from the employment of storage elements. The hardware architectures that realize the parallel processing structures are developed. The resulting architectures, which are mainly constructed of three types of standard cells, exhibit a high degree of modularity and regularity, and thus a high suitability for VLSI implementation. The architectures can process 2-D data arrays of arbitrary dimensions in real time or near real time and have higher hardware efficiency and lower implementation cost than the direct-form realization     

Suppression of transients in variable recursive digital filterswith a novel and efficient cancellation method

A new method for suppressing transients in recursive infinite impulse response (IIR) digital filters is proposed. The technique is based on modifying the state (delay) variables of the filter when coefficients are changed so that the filter enters a new state smoothly without transient attacks, as originally proposed by Zetterberg and Zhang (1988). In this correspondence, we modify the Zetterberg-Zhang algorithm to render it feasible for efficient implementation. We define a mean square error (MSE) measure for transients and determine the optimal transient suppressor to cancel the transients down to a desired level at the minimum complexity of implementation. The application of the method to all-pole and direct-form II (DF II) IIR filter sections is studied in detail. Time-varying recursive filtering with transient elimination is illustrated for tunable fractional delay filters and variable-bandwidth lowpass filters     

On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering

Many digital signal processors (DSPs) and also microprocessors are employing the single-instruction multiple-data (SIMD) paradigm for controlling their data paths. Although the SIMD paradigm can provide high computational power and efficiency, not all applications can profit from this feature. One important application, particularly in audio processing, of DSPs are recursive (IIR) filters. Due to their data-dependencies they can not exploit the capabilities of SIMD-controlled DSPs as non-recursive (FIR) filters can. This paper shows, how the SIMD control scheme can be enhanced to accommodate recursive filters without introducing much hardware overhead. Three methods for calculating recursive filters on SIMD-controlled DSPs and their requirements for control and data transfer are presented. They can be applied to direct-form as well as cascade-form realizations. The performance and hardware requirements of these methods are evaluated to determine the most efficient solution in terms of the AT-product. An erratum to this article is available at .     

Adaptive signal processing using FIR and IIR filters

A method is presented for designing optimal adaptive digital filters. The derivation is based upon filtering a desired signal which has been corrupted by a "noise" like signal so the least-square error between the filtered output and the desired output is minimized. The filter is contrasted with both the Levinson and Widrow filters. The greatest utility of the derived filters are in digital signal processing applications where real-time or stability are critical constraints.     

Broadband Beamforming Using TDL-Form IIR Filters

Conventional broadband beamforming structures make use of finite-impulse-response (FIR) filters in each channel. Large numbers of coefficients are required to retain the desired signal-to-interference-plus-noise-ratio (SINR) performance as the operating bandwidth increases. It has been proven that the optimal frequency-dependent array weighting of broadband beamformers could be better approximated by infinite-impulse-response (IIR) filters. However, some potential problems, such as stability monitoring and sensitivity to quantization errors, of the IIR filters make the implementation of the IIR beamformers difficult. In this paper, new broadband IIR beamformers are proposed to solve these problems. The main contributions of this paper include 1) the Frost-based and generalized sidelobe canceller (GSC)-based broadband beamformers utilizing a kind of tapped-delay-line-form (TDL-form) IIR filters are proposed; 2) the combined recursive Gauss-Newton (RGN) algorithm is designed to compute the feedforward and feedback weights in the Frost-based implementation; and 3) in the GSC-based structure, the unconstrained RGN algorithm is customized for the TDL-form IIR filters in the adaptive beamforming part. Compared with the beamformer using direct-form IIR filters, the new IIR beamformers offer much easier stability monitoring and less sensitivity to the coefficient quantization, while comparable SINR improvement over the conventional FIR beamformer is achieved     

General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry

Having local data communication (without global broadcast of signals) among the elements is important in very large scale integration (VLSI) designs. Recently, 2-D systolic digital filter architectures were presented which eliminated the global broadcast of the input and output signals. In this paper a generalized formulation is presented that allows the derivation of various new 2-D VLSI filter structures, without global broadcast, using different 1-D filter sub-blocks and different interconnecting frameworks. The 1-D sub-blocks in z-domain are represented by general digital two-pair networks which consist of direct-form or lattice-type FIR filters in one of the frequency variables. Then, by applying the sub-blocks in various frameworks, 2-D structures realizing different transfer functions are easily obtained. As delta discrete-time operator based 1-D and 2-D digital filters (in \(\gamma \) -domain) were shown to offer better numerical accuracy and lower coefficient sensitivity in narrow-band filter designs when compared to the traditional shift-operator formulation we have covered both the conventional z-domain filters as well as delta discrete-time operator based filters. Structures realizing general 2-D IIR (both z- and \(\gamma \) -domains) and FIR transfer functions (z-domain only) are presented. As symmetry in the frequency response reduces the complexity of the design, IIR transfer functions with separable denominators, and transfer functions with quadrantal magnitude symmetry are also presented. The separable denominator frameworks are needed for quadrantal symmetry structures to guarantee BIBO stability and thus presented for both the operators. Some limitations of having exact symmetry with separable 1-D denominator factors are also discussed.     

Reducing the Multiplier-Complexity of Massively Parallel Polyphase 2D IIR Broadband Beam Filters

The superior broadband performance of 2D IIR frequency-planar beam filters, relative to conventional 2D FIR true-time-delay beamforming, has recently been reported using computational electromagnetics and real-time emulations on an antenna test range, resulting in significant improvements of bit-error-rates (BERs) in the presence of broadband interference. Further, massively parallel systolic VLSI circuit polyphase architectures have also been reported (Madanayake et al. in Int. J. Circuit Theory Appl. 2010) for the case of the direct-form signal flow graph (SFG) architecture, operating at a maximum throughput of M-(antenna)-frames-per-clock-cycle (MFPCC). The superior broadband performance of 2D IIR frequency-planar beam filters is extended here from the direct-form signal flow graph (SFG) architecture (Madanayake et al. in Int. J. Circuit Theory Appl. 2010) to the novel differential-form SFG architecture in order to reduce overall complexity. The proposed method employs a differential-form polyphase 2D IIR frequency-planar beam SFG, and a corresponding circuit architecture, to implement the required input-output 2D space-time difference equation. The resultant digital hardware has the significant advantage of much-reduced multiplier complexity, relative to the direct-form structure. For example, when look-ahead pipelining is not employed and for polyphase architectures having two, three, and four phases, the corresponding reductions in multiplier complexity are 20%, 28.6% and 33.3%, respectively. A proof-of-concept prototype circuit is designed and implemented on a Xilinx Sx35 FPGA device for the two-phase case, operating at a frame-rate of 132 million linear frames per second on the uniform linear array (ULA), corresponding to 2-frames-per-clock-cycle at a circuit clock frequency of 66 MHz. The circuit is optimized for low critical path delays (CPDs) using look-ahead pipelining of order three. For ultra-wideband (UWB) radio-frequency (RF) implementations, in such fields as radio astronomy, radar and wireless communications, custom VLSI versions of the proposed circuits are required.     

Stability analysis of 1-D and 2-D fixed-point state-space digitalfilters using any combination of overflow and quantizationnonlinearities

A new criterion, together with its frequency-domain interpretation for the global asymptotic stability of zero-input one-dimensional (1-D) state-space digital filters under various combinations of overflow and quantization nonlinearities and for the situation where quantization occurs after summation only, is presented. A condition in closed form involving solely the parameters of the state transition matrix for the nonexistence of limit cycles in second-order digital filters is derived. Improved versions of some of the stability results due to Leclerc and Bauer (1994) are established. Finally, the approach is extended to two-dimensional (2-D) digital filters described by the Roesser and the Fornasini-Marchesini second local state-space models     

A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters

A massively parallel systolic-array architecture is proposed for the implementation of real-time VLSI spatio-temporal 3-D IIR frequency-planar filters at a throughput of one-frame-per-clock-cycle (OFPCC). The architecture is based on a differential-form transfer function and is of low circuit complexity compared with the direct-form architecture. A 3-D look-ahead (LA) form of the transfer function is proposed for maximizing the speed of the implementation, which has a nonseparable 3-D transfer function. The systolic array enables real-time implementation of 3-D IIR frequency-planar filters at radio-frequency (RF) frame-rates and is therefore a suitable building block for 3-D IIR digital filters having beam- and cone-shaped passbands as required for smart-antenna-array beam-forming applications involving the broadband spatio-temporal filtering of plane-waves. The fixed-point systolic-array implementation have a throughput of OFPCC and the tested real-time prototype achieves frame (clock) sample frequencies of up to 90 MHz using one Xilinx Virtex-4 sx35-10ff668 FPGA device.      

New criteria for asymptotic stability of one- and multidimensionalstate-space digital filters in fixed-point arithmetic

This paper addresses the problem of global asymptotic stability of one-dimensional (1-D) and multidimensional (m-D) digital filters with any combination of overflow and quantization nonlinearities. The stability analysis is carried out using 1-D and m-D state-space representations. The approach introduced allows one to determine the stability behavior of single-input single-output systems with overflow and quantization nonlinearities. The new criteria, based on previous stability results of digital filters with quantization schemes, are applicable to all arithmetic schemes. For the first time, results concerning general state variable representations of 1-D and m-D digital filters with the naturally occurring combination of two's complement truncation quantization and overflow are reported. Furthermore, significantly improved stability regions are obtained for digital filters with roundoff nonlinearities