首页 | 本学科首页   官方微博 | 高级检索  
相似文献
 共查询到17条相似文献,搜索用时 125 毫秒
1.
描述了一种新的基于单元扩大的拥挤度驱动的布局算法.这个方法用概率估计模型和星型模型来评价线网的走线.使用全局优化和划分交替的算法来进行总体布局.提出了单元的虚拟面积的概念,单元的虚拟面积不仅体现了单元的面积,而且指出了对布线资源的需求.单元的虚拟面积可以由单元的扩大策略来得到.把单元的虚拟面积用到划分过程中,从而减小拥挤度.并且使用了单元移动的策略来进一步减小走线的拥挤.用来自美国公司的一些例子测试了这个算法,结果显示布局的结果在可布性方面有了很大的提高.  相似文献   

2.
提出了一种降低走线拥挤的标准单元增量式布局算法C-ECOP.首先通过一种新型的布线模型来估计芯片上的走线情况,然后构造一个整数线性规划问题来解决可能出现的相邻拥挤区域冲突问题.实验结果表明该算法能够有效地降低走线拥挤,保证初始布局的质量,并且具有很高的效率.  相似文献   

3.
基于整数规划的优化拥挤度的增量式布局算法   总被引:2,自引:2,他引:0  
提出了一种降低走线拥挤的标准单元增量式布局算法C- ECOP.首先通过一种新型的布线模型来估计芯片上的走线情况,然后构造一个整数线性规划问题来解决可能出现的相邻拥挤区域冲突问题.实验结果表明该算法能够有效地降低走线拥挤,保证初始布局的质量,并且具有很高的效率  相似文献   

4.
提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%.  相似文献   

5.
优化时延与拥挤度的增量式布局算法   总被引:1,自引:1,他引:0  
提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10 % .  相似文献   

6.
TN4 2004050515优化时延与拥挤度的增t式布局算法/李卓远,吴为民,洪先龙(清华大学)”半导体学报一2 004,25(2)一158一164提出了一种优化时延的增量式布局算法,该算法根据时延分析的结果在迭代求解的过程中动态调整线网权值.在此基础上,提出了三种同时优化时延和拥挤度的多目标优化的布局算法,在满足时延和拥挤度约束的前提下对关键路径上的单元进行位置调整.实验结果表明该算法能够有效地提高芯片速度并降低走线拥挤.对于优化线长得到的布局方案,最长路径上的时延值在增量式布局之后能够降低10%图3表3参15(木)的散射参数解析表达式,给出了…  相似文献   

7.
针对标准单元模式超大规模集成电路增量式布局问题 ,提出了一个全新的增量布局算法 ECOP.该算法一改以往布局算法中以单元为中心的做法 ,变为以单元行为中心 ,围绕单元行来进行单元的插入 ,移动以及各种约束条件的处理 .在划分单元行时 ,始终保持单元行的内部连通性 ,并对单元移动路径进行搜索与优化 .对一组来自美国工业界的设计实例进行了测试 .实验结果表明 ,ECOP算法是非常实用而高效的  相似文献   

8.
针对标准单元模式超大规模集成电路增量式布局问题,提出了一个全新的增量布局算法ECOP.该算法一改以往布局算法中以单元为中心的做法,变为以单元行为中心,围绕单元行来进行单元的插入,移动以及各种约束条件的处理.在划分单元行时,始终保持单元行的内部连通性,并对单元移动路径进行搜索与优化.对一组来自美国工业界的设计实例进行了测试.实验结果表明,ECOP算法是非常实用而高效的.  相似文献   

9.
本文提出了一个新的Over-The-Cell通道布线算法.我们将有线问题分为两个阶段:1)单元区布线,2)通道区布线.单元区布线的目标是最大可能地减小通道密度,而不同于以在算法总企图在单元区嵌入最多的线网.文中提出了最大密度段的概念,单元区布线优先选取覆盖最大密度段的线网,这更有利于降低通道密度.布线结果只需利用较少的单元区走线道,便可有效地降低通道密度,因而增强了算法的实用性.本文提出的算法已在SUN4/110工作站上用C语言编程实现,运行结果优于国内外已发表算法的结果.  相似文献   

10.
本文提出了一种基于混合图的总体布线调整方法。混合图是对表示布局的有向图进行一系列精确的顶点分解而产生的。用得到的图模型来表示总体布线信息,从而可以在总体布局优化的同时估计布线对芯片面积的影响,并对总体布线进行调整。由于总体布线是自动更新的,所以布局同时随着布线的调整和模块的移动而改进。本文还提出了多种瓶颈的概念和瓶颈间走线随模块旋转而变化的规律。最后给出的实验结果表明,这种算法在减小芯片面积上获得比较好的结果。  相似文献   

11.
In this paper, a new hierarchical multihop routing algorithm and its performance evaluation is presented for fully dynamic wireless networks. The routing algorithm operates on a virtual topology obtained by partitioning the routing information for mobile terminals and mobile base stations into a hierarchical, distributed database. Based on the virtual topology, each mobile base station stores a fraction of the routing information to balance the complexity of the location-update and the path-finding operations. Mobility of the network entities changes the load distribution and causes processing and memory bottlenecks in some parts of the network. However, since the network routing elements are also mobile, their movement can be used to distribute the load. Thus, new load balancing schemes are intoduced to distribute the routing overhead uniformly among the mobile base stations. The performance of the hierarchical multihop routing algorithm is investigated through simulations. It is shown that the routing protocol can cope with high mobility and deliver packets to the destinations successfully.  相似文献   

12.
The authors describe a simple adaptive routing scheme for datagram (connectionless) and virtual circuit (connection-oriented) transmission that relieves congestion resulting from nonuniform traffic patterns and network failures. The authors describe a fixed-routing algorithm for dedicated channel ShuffleNets. Based on the fixed routing algorithm, an adaptive routing scheme for datagram transmission is presented followed by performance results for uniform and nonuniform traffic patterns and fault tolerance. The adaptive routing of datagrams uses only the local queue size information available at the network interface units (NIUs) and redistributes the load as congestion develops. Since datagrams are individually routed through the network, they may not arrive at their destination in the order they were generated and may need to be resequenced. The authors compute an upper estimate on the resequencing buffer size for stream traffic. A virtual circuit version of the adaptive routing algorithm eliminates the need for resequencing buffers  相似文献   

13.
Various services of internet of things (IoT) require flexible network deployment to guarantee different quality of service (QoS).Aiming at the problem of IoT service function chain deployment,network function virtualization (NFV) and software defined networking (SDN) were combined to optimize resources.Considering forwarding cost and traffic load balance,a joint optimization model of virtual network function placement and service function chain routing was given and was proved to be NP-Hard.In order to solve this model,two heuristic algorithms were proposed.One was the service chain deployment algorithm of first routing then placing (FRTP) and the other was the placing followed by routing (PFBR) based on node priority.Simulation results demonstrate that FRTP and PFBR algorithm can significantly balance network traffic load while alleviating congestion and improving the acceptance ratio of the chain requests compared with other algorithms.  相似文献   

14.
An efficient heuristic force directed placement algorithm based on partitioning is proposed for very large-scale circuits. Our heuristic force directed approach provides a more efficient cell location adjustment scheme for iterative placement optimization than the force directed relaxation (FDR) method. We apply hierarchical partitioning based on a new parallel clustering technique to decompose circuit into several level sub-circuits. During the partitioning phase, a similar technique to ‘terminal propagation’ was introduced so as to maintain the external connections that affect cell adjustment in sub-circuit. In these lowest level sub-circuits, the heuristic force directed algorithm is used to perform iterative placement optimization. Then each pair of sub-circuits resulted from bisection combine into a larger one, in which cells are located as the best placement state of either sub-circuits. The bottom-up combination is done successively until back to the original circuit, and at each combination level the heuristic force directed placement algorithm is used to further improve the placement quality. A set of MCNC (Microelectronics Centre of North-Carolina) standard cell benchmarks is experimented and results show that our placement algorithm produces on average of 12% lower total wire length than that of Feng Shui with a little longer CPU time.  相似文献   

15.
《Microelectronics Journal》2007,38(8-9):942-958
Routing congestion is a critical issue in deep submicron design technology and it becomes one of the most challenging problems in today's design flow. In this paper, various congestion-related metrics were defined and evaluated during placement stage of physical design flow. Our experiments show that the overflow metric results are more accurate than others. In addition, the bend distributions after detailed routing for IBM-PLACE benchmarks were extracted and used to guide a pure probabilistic method. Furthermore, router's behavior for congestion minimization was modeled and used to propose a true congestion prediction algorithm. Experimental results show that the proposed algorithm estimates the congestion more accurately than a commonly used method by about 21% on average. Additionally, a new congestion reduction algorithm is presented based on contour plotting. Our experiments show that our algorithm reduces the peak congestion by about 25% on average. In addition, comparing our results with a recent approach shows that our technique reduces congestion more by about 10% on average. In order to evaluate the results of white space allocations on the quality of our reduction technique, several other experiments were attempted. Various amounts of white space were added to several IBM-PLACE benchmarks and the contour plotting-based reduction technique was used to reduce the peak and average congestion. The experiments show that our technique works better on the benchmarks with more white space as it has more capability to distribute routing congestion evenly.  相似文献   

16.
Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.  相似文献   

17.
In an era of sub-micron technology, routing is becoming a dominant factor in area, timing, and power consumption. In this paper, we study the problem of selection and chaining of scan flip-flops with the objective of achieving minimum routing area overhead. Most of previous work on partial scan has put emphasis on selecting as few scan flip-flops as possible to break all cycles in S-graph. However, the flip-flops that break more cycles are often the ones that have more fanins and fanouts. The area adjacent to these nodes is often crowded in layout. Such selections will cause layout congestion and increase the number of tracks to chain the scan flip-flops. To take layout information into consideration, we propose a matching-based algorithm to solve the problem. First, an initial placement will be performed before scan flip-flops are selected. Then, iteratively, a matching-based algorithm taking the current layout into account is proposed to select and chain the scan flip-flops. Experimental results show that, on the average, our algorithm can reduce 8.1% area overhead as compared with the previously proposed methods that do not utilize the layout information in flip-flop selection.  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号