Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO₂) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.     

Noise in semiconductor laser amplifiers with quantum box structure

The low-noise properties of a quantum-box traveling-wave semiconductor laser amplifier (QB-TW-SLA) are discussed. The gain and population-inversion parameter of a quantum-box structure are precisely expressed using density matrix theory. Due to sharp gain characteristics as well as a small population inversion parameter, dominant two-beat noise is significantly reduced, even in a solitary device without a narrow bandpass filter. The noise figure can be reduced to 3.5 dB     

Noise study of low-dimensional quantum-well semiconductor laseramplifiers

Low noise characteristics of semiconductor laser amplifiers (SLAs) consisting of low-dimensional quantum-well structures are obtained theoretically using density matrix theory. Due to a sharper gain spectrum as well as a smaller population inversion parameter in quantum-wire and quantum-box structures, predominant two beat noises of traveling-wave SLAs were found to be reduced in the lower dimensional quantum-well structures, even in solitary devices without a narrow bandpass filter. The noise figure can be reduced to 3.3 dB in a quantum-box structure, which nears the theoretical limit of 3 dB     

The MOS inversion layer as a minority carrier injector

In this paper we report the first experimental demonstration of the concept of MOS inversion layer injection (ILI). The new physical concept is based on the use of a MOS inversion layer as a minority carrier injector as part of a dynamic junction. The carrier injection of such a junction is entirely controlled by the MOS gate. Moreover, when the gate potential is reduced under the MOS threshold voltage, the junction collapses ensuring a very efficient turn-off mechanism. Based on this concept we propose two novel lateral three-terminal structures termed inversion layer diode (ILD) and inversion layer bipolar transistor (ILBT). The concept of inversion layer injection can be applied in power devices where effective MOS gate control of the active junctions is important     

The Effect of Single-Halo Doping on the Low-Frequency Noise Performance of Deep Submicrometer MOSFETs

In this letter, the low-frequency noise performance of single-halo (SH) devices is reported, and the physical mechanisms are identified. Experimental results show that, at constant gate overdrive voltages, SH devices show reduced low-frequency noise levels compared to the conventional devices. However, under constant current bias conditions, the noise reduction is less substantial. Low-frequency noise dependence on channel length is also investigated for SH devices based on the electrical measurements and analytical calculations     

器件结构和材料质量对GaAs MESFET噪声系数的影响

本文从栅源串联电阻R_s和有效栅长L_f两方面论述了深槽自对准斜蒸栅结构可明显减小R_s与缩短L_f,有利于降低器件的噪声系数。 本文还用相关栅长L_a和器件在低温下的性能说明GaAs材料的质量对器件噪声系数的影响。提高GaAs半绝缘衬底和缓冲层质量以及与有源层交界面附近的迁移率,可较明显地缩短相关栅长L_a,降低器件噪声。 采用这一器件结构,并选用质量较高的GaAs材料,制得的MESFET,在12GHz下相关增益G_a为7.5dB,噪声系数NF_(min)为1.4dB,与理论预计值相符。     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

AlSb/InAs HEMT's for low-voltage, high-speed applications

The design, fabrication, and characterization of 0.1 μm AlSb/InAs HEMT's are reported. These devices have an In_0.4Al _0.6As/AlSb composite barrier above the InAs channel and a p ⁺ GaSb layer within the AlSb buffer layer. The HEMT's exhibit a transconductance of 600 mS/mm and an f_T of 120 GHz at V_Ds=0.6 V. An intrinsic f_T of 160 GHz is obtained after the gate bonding pad capacitance is removed from an equivalent circuit. The present HEMT's have a noise figure of 1 dB with 14 dB associated gain at 4 GHz and V_Ds=0.4 V. Noise equivalent circuit simulation indicates that this noise figure is primarily limited by gate leakage current and that a noise figure of 0.3 dB at 4 GHz is achievable with expected technological improvements. HEMT's with a 0.5 μm gate length on the same wafer exhibit a transconductance of 1 S/mm and an intrinsic f_TL_g, product of 50 GHz-μm     

Design Guidelines for the Noise Optimization of a 0.18 μm CMOS Low-Noise Amplifier

This paper presents the design considerations for the noise optimization of fully integrated tuned low-noise amplifiers (LNA) based on the four noise parameters and two-port noise theory. Specifically, this paper provides the design guidelines for a 0.18 μm CMOS tuned LNA. These guidelines give a useful indication to the design tradeoffs associated with noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology. As a case study, a 10 GHz LNA has been designed using 0.18 μm CMOS technology for a wireless LAN application. The amplifier has a 2.4 dB noise figure with a −13 dBm third-order input intercept point, while drawing 5 mW from a 1.8 V power supply. The results show that the proposed theoretical contours of constant noise figure which relate the gate overdrive voltage and power dissipation can accurately predict the noise performance of a 0.18 μm CMOS LNA design Ahmed A. Youssef received the B.Sc. (Hon.) and M.Sc. degrees both in electrical engineering from Ain Shams University, Cairo, Egypt, in 1998 and 2002, respectively. Since 2003, he has been with the University of Calgary, AB, Canada, where he is currently working toward the Ph.D. degree in RF integrated circuits and systems. Mr. Youssef has joined the Wireless Research Center at TRLab, Alberta, Canada as a research associate in 2004. His research interests include the analog high speed integrated circuit for the wireless LAN applications. Mr. Youssef is the recipient of the Mobinil Telecommunication Inc. Pre-master Fellowship in 1999. He also received the Young Scientist award at the Maastricht General Assembly of the International Union of Radio Science in 2002 and an Honorable Mention at 2003 in the Symposium of the Microelectronics Research & Development in Canada, Montreal. Mr. Youssef received the Gordon Lewis Hedberg Doctoral Scholarship in 2005.     

DC and microwave characteristics of sub-0.1-μm gate-lengthplanar-doped pseudomorphic HEMTs

Analytical modeling of these very-short-channel HEMTs (high-electron-mobility transistors) using the charge-control model is given. The calculations performed using this model indicate a very high electron velocity in the device channel (3.2±0.2×10⁷ cm/s) and clearly demonstrate the advantages of the planar-doped devices as compared to the conventional uniformly doped HEMTs. Devices with different air-bridged geometries have been fabricated to study the effect of the gate resistance on the sub-0.1-μm HEMT performance. With reduced gate resistance in the air-bridge-drain device, noise figures as low as 0.7 and 1.9 dB were measured at 18 and 60 GHz, respectively. Maximum available gains as high as 13.0 dB at 60 GHz and 9.2 dB at 92 GHz, corresponding to an f_max of 270 GHz, have also been measured in the device. Using the planar-doped pseudomorphic structure with a high gate aspect-ratio design, a noise figure of less than 2.0 dB at 94 GHz is projected based on expected further reduction in the parasitic gate and source resistances     

Design of Low Power 2.4GHz CMOS Cascode LNA with Reduced Noise Figure for WSN Applications

In this paper, a narrowband cascode Low Noise Amplifier (LNA) with shunt feedback is proposed. A typical inductively degenerated cascode LNA can be treated as a Common Source-Common Gate (CS-CG) two stage LNA. The series interstage inductance is connected between CS-CG stages to increase the power gain. An additional inductance which is connected at the gate of CG stage is used to cancel out the parasitic capacitance of CG stage therefore reduces the noise figure of CG stage. The shunt feedback is used to improve the stability and input impedance matching. This configuration provides better input matching, lower noise figure, low power consumption and good reverse isolation. The proposed LNA exhibits the gain of 13 dB, input return loss of ?11 dB, noise figure of 2.2 dB and good reverse isolation of ?42.8 dB at a frequency of 2.4GHz using TSMC 0.13 μm CMOS technology. It produces gain and noise figure better than conventional cascode LNA. The proposed LNA is biased in moderate inversion region for achieving sufficient gain with low power consumption of 1.5mW at a supply voltage of 1.5V.     

Microwave performance of 0.25-µm gate length high electron mobility transistors

The performance of 0.25-µm gate length high electron mobility transistors (HEMT's) is reported. Devices were fabricated on layers grown by MBE. One of the heterostructures had no undoped AlGaAS spacer layer (wafer A), whereas the other had a 40-Å spacer layer (wafer B). The maximum stable gain on both wafers was ∼ 12 dB at 18 GHz. The minimum noise figure measured was 0.60 dB at 8 GHz and 1.3 dB at 18 GHz. Wafer A yielded devices with a unity current gain cutoff frequency ftof 65 GHz whereas wafer B gave an ftof 70 GHz. These results can be attributed primarily to the high quality material, low parasitic resistance, and short gate length.     

Noise reduction in single channel radio bearers employing privacy

Frequency inversion of the voice spectrum is a common method of providing simple privacy on single channel radio links. When combined with exponential modulation this method produces an increase in system noise of 8.00 dB. Alternative inversion methods are analyzed. The methods involve partitioning the voice spectrum into two halves, inverting one or both of these halves and, in some cases, incorporating a bandshift. The optimum method, entitled "dual inversion with down-shift," reduced the increase in system noise performance to 0.99 dB for a small increase in residual intelligibility. This was measured at 36 percent using a voice test incorporating digit identification. Frequency inversion had a residual intelligibility of 31 percent.     

Low-temperature characterization of buried-channel NMOST

A comprehensive characterization of buried-channel NMOS transistors at low temperatures down to 30 K is reported. The mobilities of both surface (accumulation) and bulk (buried-channel) electrons were determined as a function of surface electric field and gate bias voltage, respectively, at low temperatures. Both surface electron mobility and buried-channel electron mobility increase with decreasing temperatures. However, a peak in the buried-channel electron mobility is observed around 80 K if the neutral region extends to regions of high impurity concentrations near the surface. A modified MOSCAP (Poisson solver) was used to obtain spatial distributions of carriers and to predict the C-V curves. Low-frequency noise measurements at low temperatures were carried out at gate voltages corresponding to the accumulation, depletion, and inversion modes of operation of the device. In the accumulation mode, a 1/f dependence is observed similar to surface-channel devices. In the depletion mode, a generation-recombination type of noise is observed with a peak around 150 K. In the inversion mode, noise that is related to the hole inversion layer is observed     

Impact of negative bias temperature instability on digital circuit reliability

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.     

Double-pass L-band EDFA with enhanced noise figure characteristics

A new double-pass long wavelength band erbium-doped fiber amplifier with enhanced noise figure characteristics is demonstrated by adding a short length of forward pumped erbium-doped fiber (EDF) in front of a double-pass amplifier. Compared with the conventional double-pass amplifier, the new amplifier provides noise figure improvement of about 0.8 to 6.0 dB over the flat-gain region from 1568 to 1600 nm. Since the optical circulator prevents the amplified signal and backward amplified spontaneous emission from propagating into the EDF, the population inversion of the input part of the amplifier is hardly affected by the intense lights, therefore, the noise figure could be kept low. The new double-pass system has achieved a flat-gain output at about 33.5 dB, which is 13.5 dB higher than that of the single-pass system with gain variation less than 1.3 dB at the flat-gain region. The noise figure varies from 5.9 to 6.6 dB in this region.     

Transimpedance amplifier with 120 dB dynamic range

A transimpedance amplifier (TIA) with compression of the input current is presented. The proposed TIA has two regions of operation: a linear one for small input currents and one with compression for high currents, which would otherwise saturate the TIA. The measured -3 dB bandwidth is 102 MHz, the equivalent RMS input current noise is 20.2 nA and the maximal current overdrive is 20.5 mA, leading to a dynamic range at the input of 120 dB     

2～40GHz PHEMT小信号等效电路模型

在基本等效电路模型基础上考虑了栅、源、漏引线分布效应、射频耦合效应及偶极层电容，用此模型模拟了Ｘ－４１管芯２～４０ＧＨｚ范围内的微波Ｓ参数，结果和测试结果吻合很好。还给出了偶极层电容和电极问射频耦合电容半经验公式。以此模型为基础，设计了１８～３６ＧＨｚ宽频带前置放大匹配电路。经优化得到：增益≥５ｄＢ，噪声≤３．２ｄＢ，增益平坦度≤±０．２５ｄＢ，达到设计要求。     

Application of anodization in Oxygen plasma to fabrication of GaAs IGFET's

Anodic oxide grown in oxygen plasma has been used to fabricate the gate insulator of GaAs insulated-gate field-effect transistors (IGFET's), by patterning the gate electrode of 1.2 µm in length with the dry etching process. It is found that the oxidation process does not damage the electrical property of the channel layer. However, the trap states at the interface between the oxide and the channel affect the low-frequency characteristics, especially at positive gate voltage. The IGFET's show a good high-frequency performance comparable to GaAs MESFET's. The following characteristics are confirmed from the measurement of the S-parameters and the equivalent circuit analysis; the maximum stable power gain is 11.4 dB at 8 GHz, the cut-off frequency of the unilateral power gain is 48 GHz, and the intrinsic gain-bandwidth product is 18 GHz. The minimum noise figure is measured to be 4.8 dB at 8 GHz.     

Very low-voltage digital-audio ΔΣ modulator with 88-dBdynamic range using local switch bootstrapping

A 1-V 1-mW 14-bit ΔΣ modulator in a standard CMOS 0.35-μm technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz