微电子学、集成电路

TN4 00060471基于重定时的高性能控制电路间接测试生成方法/黄祖兰,叶以正(哈尔滨工业大学)11电子学报一2 000。28(2).一83、86对性能驱动控制逻辑进行测试生成难度较大,通常要加人可测性结构,但会影响原电路优化性能并增加生产成本.文中以重定时理论为基础,提出了对高性能时序电路进行间接测试生成的方法,这种方法在不影响原电路任何优化特性的前提下,可显著降低测试生成时间,提高测试生成质量.在15 CAS’89部分基准电路进行实验,结果证明了其有效性图3表2参7(金)TN4 00060474P DP中的新型保护膜/贾正根(南京电子器件所)刀光电子技术‘…     

基于探索式分区和测试向量生成的硬件木马检测方法

本文提出基于分区和最优测试向量生成的硬件木马检测方法.首先,采用基于扫描细胞分布的分区算法将电路划分为多个区域.然后,提出测试向量重组算法,对各区域依据其自身结构生成近似最优的测试向量.最后,进行分区激活和功耗分析以检测木马,并采用信号校正技术消减制造变异和噪声的影响.优点是成倍提高了检测精度,克服了制造变异的影响,解决了面对大电路的扩展性问题,并可以定位木马.在基准电路上的验证实验表明检测性能有较大的提升.     

组合电路桥接故障诊断的测试生成及优化

在利用划分等价类的方法来诊断组合电路中桥接故障的基础上,本文提出了一种基于门特性的IDDQ测试集生成算法及对测试集排序筛选的优化方法.实验结果表明,将此方法应用于组合电路桥接故障的诊断可缩减测试集的大小,提高诊断的故障覆盖率.     

边界扫描测试的自适应完备诊断算法的优化

IEEE1149.1边界扫描机制是一种新型的VLSI电路测试及可测性设计方法,在边界扫描测试过程中生成合理的测试向量集是有效应用边界扫描机制对电路系统进行测试的关键。在分析传统边界扫描测试生成算法和W步、C步自适应测试生成算法的基础上,提出了一种改近的自适应测试生成算法。实验表明该算法具有完备的诊断能力和紧凑性指标较低的优点,是一种性能优良的完备测试生成算法。     

具有邻域子空间的电路模块的高效测试生成

对于VLSI中具有邻域子空间的电路模块,提出了一种高效测试生成方法.利用该方法得到了行波进位、超前进位加法器的测试生成,并予以了硬件实现.8位、16位和32位两种加法器的测试实验表明,这些测试生成能够使单固定型故障的故障覆盖率达到100%,双故障覆盖率分别达到99.996%以上以及100%,故障定位率得到了显著提高.测试矢量的数目仅与邻域子空间的大小有关.由于原电路中加法器的复用,两种加法器测试生成的硬件实现仅需额外的一个逻辑与门,将硬件开销降至最小.     

低功耗单输入跳变测试理论的研究

介绍一种随机单输入跳变(RSIC)低功耗测试方案.基本原理是在原线性反馈移位寄存器(LFSR)的基础上加入代码转换电路,对LFSR输出的随机测试向量进行变换,从而得到随机单输入跳变测试序列,可以在不损失故障覆盖率的前提下,降低被测电路的开关翻转活动率,实现测试期间的低功耗.文中给出了RSIC测试序列的生成准则,以CC4028集成电路为被测电路作了研究,结果表明在进行低功耗测试时,单输入跳变测试序列比多输入跳变测试序列更加有效,在不影响故障覆盖率的情况下可以将开关翻转活动率降低到58%,证实了该方案的实用性.     

FD—Ⅲ—一个数字电路层次式测试生成系统

本文介绍一个实用数字集成电路层次式测试图形自动生成（ＡＴＰＧ）系统－ＦＤ－Ⅲ。ＦＤ－Ⅲ的特点是把测试生成和电路设计结合起来，充分利用电路的层次式结构，借助于电路和功能块已有的测试和模拟结果，加快整个电路的测试生成。该系统能对由ＷｏｒｋＶｉｅｗ等ＣＡＤ系统描述的层次式组合电路，同步时序电路进行ＡＴＰＧ。其故障模拟（ＦＳ）子系统能对包括异步模块在内的电路进行故障模拟、测试压缩，并给出优化的测试集及其性     

数字电路测试生成中的几种仿生优化算法

数字集成电路的快速发展对电路测试提出了日益紧迫的要求，为获得较好的数字电路的故障覆盖率和测试集，减少反向回溯，很多仿生学算法应用到了电路的测试生成当中，现介绍了在测试生成领域中有重大影响的几种仿生优化算法以及各自特点。     

基于蚁群算法的测试集优化

电路集成度和复杂度的不断增加使电路故障诊断变得愈加困难.其中,测试集优化问题是电路故障诊断的关键问题之一.本文以新颖的蚁群算法为基础,较好地解决了测试集的优化问题,并通过实验证明了该算法的良好性能.     

数字电路测试向量自动生成系统的比较

把遗传算法与蚂蚁算法运用于组合电路向量自动生成系统,并比较两者性能的优劣,根据实验结果进一步提出优化组合方案,将此方案应用于同步时序电路的测试向量自动生成系统中。提出一种优化的数字电路的测试向量自动生成系统。这个系统集合了蚂蚁算法和遗传算法的优点,使系统能在更短时间生成更小的测试集,而又能达到原先的故障覆盖率。     

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.     

New Techniques for Deterministic Test Pattern Generation

This paper presents new techniques for speeding up deterministic test pattern generation for VLSI circuits. These techniques improve the PODEM algorithm by reducing number of backtracks with a low computational cost. This is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. We have incorporated these techniques into an advanced ATPG system for combinational circuits, called ATOM. The performance results for the ISCAS85 and full scan version of the ISCAS89 benchmark circuits demonstrated the effectiveness of these techniques on the test generation performance. ATOM detected all the testable faults and proved all the redundant faults to be redundant with a small number of backtracks in a short amount of time.     

A novel automatic test pattern generator for asynchronous sequential digital circuits

A novel automatic test pattern generator (ATPG) for stuck-at faults of asynchronous sequential digital circuits is presented. The developed ATPG does not require support by any design-for-testability method nor external software tool. The shortest test sequence generation is guaranteed by breadth-first search. The contribution is unique hazard identification before the test generation process, state justification on the gate level, sequential fault propagation based on breadth-first search and stepwise composition of state graphs for sequential test generation. A new six-valued logic together with a new algorithm was developed for hazardous transition identification. The internal combinational ATPG allows to generate test patterns one by one and only if it is required by sequential test generation. The developed and implemented ATPG was tested with speed-independent and quasi-delay-insensitive benchmark circuits.     

Low-power multi-core ATPG to target concurrency

A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency.     

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency

This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all the techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware DL to uniquely identify a state appearing in a state register. The design of DL is universal. Test length and hardware overhead outperform the similar approaches.     

Sequential circuit test generation using dynamic justification equivalence

Automatic test pattern generation (ATPG) for sequential circuits involves making decisions in the search decision spaces bounded by a sequential circuit. The flip-flops in the sequential circuit determine the circuit state search decision space. The inputs of the circuit define the combinational search decision space. Much work on sequential circuit ATPG acceleration focused on how to make ATPG search decisions. We propose a new technique to improve sequential circuit ATPG efficiency by focusing on not repeating previous searches. This new method is orthogonal to existing deterministic sequential circuit ATPG algorithms.A common search operation in sequential circuit ATPG is justification, which is to find an input assignment to justify a desired output assignment of a component. We have observed that implications in a circuit resulting from prior justification decisions form an unique justification decomposition. Since the connectivity of a circuit does not change during ATPG, test generation for different target faults may share identical justification decision sequences represented by identical decision spaces. Because justification decomposition represents the collective effects of prior justification decisions, it is used to identify previously-explored justification decisions. Preliminary results on the ISCAS 1989 circuits show that our test generator (SEST) using justification decompositions, on average, runs 2.4 and 4.5 times faster than Gentest and Hitec, respectively. We describe the details of justification equivalence and its application in ATPG accompanied with step-by-step examples.     

论有限回溯测试模式产生方法

本文首先剖析了有限回溯测试模式产生(FBTPG)方法的实质,然后在深入分析三种ATPG系统的C-B曲线的实验数据的基础上,提出故障模拟对测试生成的综合调节效应,为FBTPG方法的有效性提供了理论依据.最后以ISCAS-85和ISCAS-89电路为基础,给出了FBTPG与随机测试生成、确定性测试生成和商用ATPG系统FlexTest的实验比较结果,从而论证了FBTPG方法处理超大规模时序电路的有效性.     

DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.     

Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays

Test and validation of embedded array blocks remains a major challenge in today's microprocessor design environment. The difficulty comes from twofold, the sizes of the arrays and the complexity of their timing and control. This paper describes a novel test generation methodology for test and validation of microprocessor embedded arrays. Unlike traditional ATPG methods, our test generation method is based upon the high-level assertion specification which is originally used for the purpose of formal verification. The superiority of these assertion tests over the traditional ATPG tests will be discussed and shown through various experiments on recent PowerPC microprocessor designs.     

基于故障插入的电路抗老化输入矢量生成研究

随着CMOS工艺特征尺寸的不断缩小,晶体管的老化效应严重影响了电路的可靠性,负偏置温度不稳定性(NBTI)是造成晶体管老化的主要因素之一。提出了一种基于固定故障插入的电路抗老化输入矢量生成方法,在电路的合适位置插入固定故障,通过自动测试向量生成(ATPG)工具获取较小的备选抗老化矢量集合,再从中筛选出最优矢量。由该方法生成的输入矢量可以使电路在待机模式下处于最大老化恢复状态,同时具有较小的时间开销。在ISCAS85电路中的仿真结果表明,与随机矢量生成方法相比,在电路待机模式下加载本文方法生成的输入矢量,可以达到最高17%的电路老化时延改善率。