基于VHDL语言的数字电路测试码自动生成

本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。在VHDL语言描述组合数字电路的基础上,建一VHDL语言的编译器,并输入为描述被测电路的VHDL语言,输出结果为描述被测电路功能的一系列逻辑表达式。针对这些逻辑表达式,本文详细地介绍了一种能直接产生电路测试码的算法。     

基于遗传算法的数字电路测试生成方法

本文提出了一种基于遗传算法的数字电路测试图形生成方法，首先把被测电路的门级描述转化为易于计算的非线性网络，然后用遗传算法找到网络能量函数的最优解，从而得到被测电路的测试集．这种方法对可测故障都能生成测试，能方便地产生多故障的测试图形，同时具有较好的并行性，易于在多处理机上实现．     

基于改进Transformer的电信重投报告自动生成方法研究

在电信行业中,客户对未解决或处理不满意的投诉进行重复投诉的现象较为常见。手动生成重投报告不仅耗时且主观性较强,难以满足企业对高效性和一致性的要求。针对这一问题,提出了一种基于改进Transformer模型的自动化报告生成方法。该方法通过引入情绪嵌入,有效捕捉客户在对话中的情绪变化,改善了生成报告对客户态度和诉求的理解能力。同时,结合定制化位置编码,提升了模型对投诉时序信息的感知能力,从而增强了生成内容的时间逻辑性和细节完整性。实验结果表明,改进后的模型在BLEU(bilingual evaluation understudy)和ROUGE (recall-oriented understudy for gisting evaluation)指标上分别达到0.352和0.482,显著优于原始Transformer和其他对比模型。此外,与人工对比,工作效率提高了89%。生成的报告内容不仅更加准确贴合实际需求,还在语义细节与时序一致性上表现优异。     

基于结构的行为级测试生成

本文针对固定型单故障,讨论了不同结构的、任意位全加器的测试生成问题。对于串行进位的全加器,只需8个测试码就可得到100％的故障覆盖率;对于n位先行进位全加器,则需要2~(n 2) 2~n-n 4个测试码。     

可执行测试套的自动生成

本语文介绍了基于ＵＮＩＸ网络环境的可执行测试套的自动生成的具体实现。     

结合结构特征基于测试集重排序的故障诊断方法

故障诊断是集成电路领域中的重要研究方向,基于测试激励集方法求解候选故障诊断是目前较为高效的诊断方法,而GTreord是目前具有较高诊断准确性的方法.在对GTreord方法深入研究的基础上,本文依据测试激励与候选故障诊断解之间的结构特征,通过分析电路故障输出响应,提出结合结构特征的测试激励集重排序的候选诊断(Reor-d...     

基于遗传算法的自适应测试生成

文章介绍了一种基于遗传算法的自适应测试生成方法，首先讨论了用遗传算法进行测试生成时构造评价函数的一些方法，然后应用组合电路的Hopfield神经网络模型，提出了基于遗传算法的自适应测试生成算法，该方法不同于传统的方法，它不需要故障传播传播、回退等过程，实验结果表明了本算法的可行性。     

基于变周期重播种LFSR的测试生成

基于重播种的LFSR结构的伪随机测试生成中包含的冗余测试序列较多,因而其测试序列长度仍较长,耗费测试时间长,测试效率不高.针对此状况,提出基于变周期重播种的LFSR结构的测试生成方法.该方法可以有效地跳过伪随机测试生成中的大量冗余测试序列.在保证电路测试故障覆盖率不变的条件下,缩短总测试序列的长度.分析结果表明,同定长重播种方法相比,该方法能以较少的硬件开销实现测试序列的精简,加快了测试的速度,提高了电路测试诊断的效率.     

基于神经网络模型测试生成的学习策略

本文描述一种基于组合电路的Ｈｏｐｆｉｅｌｄ神经网络模型的测试生成系统，重点介绍了系统中实现神经网络学习并记忆基于电路拓扑的知识信息的学习策略，从而将基于电路拓扑的知识与数学计算结合起来，最后给出了实验结果。     

关于再定时对于E1时钟传送性能影响的测试及分析

阐述了SDH的E1支路"再定时"功能,指出目前业内基本不采用的现实情况,并通过实际测试验证"再定时"对于提高时钟信号质量的效果,详细介绍了测试的步骤和方法,并提出明确的建议。     

Testing the Local Interconnect Resources of SRAM-Based FPGA's

This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs. First, it is demonstrated that a n address bit Configurable Interface Multiplexer requires N = 2 ⁿ test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analyzed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N = 2 ⁿ . Third, it is shown that the complete circuit i.e. a m × m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N = 2 ⁿ test configurations using the XOR tree and shift register structures.     

State and Fault Information for Compaction-Based Test Generation

We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vector compaction. Two types of techniques are considered. One is based on the new states a sequential circuit is driven into, and the other is based on the new faults that are detected between consecutive iterations of vector compaction. These data modify an otherwise random selection of vectors, to bias vector sequences that cause the circuit to reach new states, and cause previously undetected faults to be detected. The biased vectors, when used to extend the compacted test set, provide a more intelligent selection of vectors. The extended test set is then compacted. Repeated applications of state and fault analysis, vector generation and compaction produce significantly high fault coverage using relatively small computing resources. We obtained improvements in terms of higher fault coverage, fewer vectors for the same coverage, or smaller number of iterations and time required, consistently for several benchmark circuits.     

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m × m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.     

一种高性能数字下变频硬件计算结构

数字下变频是软件无线电的核心技术,随着通信技术的发展,如今对其处理速度要求越来越高。现提出了一种高性能的数字下变频硬件计算结构,使用CORDIC,流水线划分,重定时等技术来优化数字下变频各个模块的硬件结构。通过和传统设计方案的实验比较,证明了本方案能在将FPGA总体资源使用等效门数减少29．54％的情况下,将最高数据吞吐率提升6．74倍。     

Selection of Crosstalk-Induced Faults in Enhanced Delay Test

Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. In this paper, we address the problem of enhanced delay test considering crosstalk-induced effects. Two types of crosstalk-induced delay fault model in related works are analyzed according to their relationship to common delay fault models. The difficulties in test generation using these fault models are shown. Based on the discussion, a single precise crosstalk-induced path delay fault model, S-PCPDF model, is proposed for circuits given delay assignment. A target S-PCPDF fault gives information on a sub-path to be sensitized to generate necessary transitions coupled to a critical path. It is then convenient to enhance conventional path delay fault ATPG algorithms to implement ATPG systems for crosstalk-induced path delay faults by adding the constraints on the sub-path. We then propose two approaches to reducing the number of target S-PCPDF faults. One is based on constraints for side-inputs of paths under test. The other is based on pre-specified states during test generation for the critical path. Experimental results on ISCAS89 benchmark circuits showed that the proposed approaches can reduce the number of target faults significantly and efficiently. The CPU time for fault list reduction and test pattern generation is acceptable for circuits of reasonable sizes.Huawei Li received her B.S. degree in computer science from Xiangtan University in 1996, and M.S. and Ph.D. degrees from the Institute of Computing Technology, Chinese Academy of Sciences in 1999 and 2001 respectively. She is now an associate professor at the Institute of Computing Technology, Chinese Academy of Sciences. Her research interests include VLSI/SoC design verification and test generation, delay test, and dependable computing.Xiaowei Li received his B.Eng. and M.Eng. degrees in computer science from Hefei University of Technology (China) in 1985 and 1988 respectively, and his Ph.D. degree in computer science from the Institute of Computing Technology, Chinese Academy of Sciences in 1991. Dr. Li joined Peking University (China) as a Postdoctoral Research Associate in 1991, and was promoted to Associate Professor in 1993, all with the Department of Computer Science and Technology. From 1997 to 1998, he was a Visiting Research Fellow in the Department of Electrical and Electronic Engineering at the University of Hong Kong. In 1999 and 2000, he was a Visiting Professor in the Graduate School of Information Science, Nara Institute of Science and Technology, Japan. He Joined the Institute of Computing Technology, Chinese Academy of Sciences as a professor in 2000. At present, he is a vice-director of the laboratory of information networks. His research interests include VLSI/SoC design verification and test generation, design for testability, low-power design, dependable computing. Dr. Li received the Natural Science Award from the Chinese Academy of Sciences in 1992, the Certificate of Appreciation from IEEE Computer Society in 2001. He is a senior member of IEEE and a senior member of China Computer Federation. He is an editor of Journal of Computer Science and Technology and Journal of Computer-Aided Design & Computer Graphics (in Chinese).     

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called pseudo shift register for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called shifted MATS++ is described.