MPDL0802型数控延迟线研究

本文论述了８位数控延迟线的设计原理，电路框图和采用的工艺，研究过程中解决的技术难点，其中包括８位数控延迟线的设计、延迟网络的设计、延迟量的调整、环境温度对延迟量的影响等。给出了解决这些问题的措施以及还存在的问题。     

有问有答

问1:一台松下NV-370录像机无彩色但黑白图像清晰。用万用表检查色度电路和亮度电路,直流电位基本正常;用示波器检查发现,色度处理电路IC8001脚18输出的色度信号接至2行延迟线脚2的波形与幅度正常(1.5V_(P-P)),但色度延迟线脚3输出V_(P-P)只有10mV(正常值应为0.3V_(P-P)),查外围元件均好,延迟线也未发现短路。问该故障是否因延迟线不良引起,是否可用彩电1行延迟线代替?     

基带延迟线彩色解码电路原理与分析

基带延迟线彩色解码电路原理与分析电路分析湖北襄樊市通达集团公司电视设计所吕献平随着微电子技术的发展，越来越多的新电路及其新器件应用于彩色电视接收机电路，其中使用基带延迟线（ＢａｓｅＢａｎｄＤｅｌａｙＬｉｎｅ）进行彩色信号解调，代替以往的玻璃超声延迟线...     

一款宽带实时延迟线芯片的设计和实现

为降低电子系统在宽带运用中波束倾斜效应的影响,开展了相关的技术研究。简要介绍了实时延迟线电路的基本概念,对电路设计流程进行了阐述。最终成功开发出一款具有小尺寸和优异微波性能的GaAs微波单片集成数控实时延迟线电路。其性能指标为:工作频率2～8GHz,插入损耗≤23dB,总延时量为637.5ps,驻波比≤1.5∶1。同时指出,要获得高精度的实时延迟线芯片,正确选择控制器件的连接方式和分析延时网络的寄生效应是必要的。     

用差动式SAW延迟线(由MOSFET控制)的可调SAW振荡器的研究

报导了用SAW差动延迟线构成的可调SAW振荡器的理论与实验研究结果。差动延迟线是由金属氧化物半导体场效应晶体管(MOSFET)电路来控制的。给出了70MHz SAW振荡器实验电路的详细情况,其中包括可调谐性和相位噪声特性。由于利用了这种MOSFET控制电路,从而使这种调谐技术有可能用于超高频(UHF)SAW振荡电路。     

横向均衡器的容差分析

在大容量数字微波通信系统中,常用基带自适应横向均衡器来克服由于多径效应引起的频率选择性衰落。均衡器中延迟线电路的设计和制作是整个均衡器的一个重要环节。本文讨论了用LC全通网络实现的延迟线单元电路,以及在设计和制作中,延时误差和幅频失真对均衡器的均衡能力及整个系统的误码率性能的影响。     

瞬时测频(IFM)接收机的试验与评价

前言 IFM接收机用延迟线把频率变换为相位差进行测频。对任何特定频率编码所用的时间与最长延迟线和频率检测电路有关。2～4千兆赫接收机典型的编码时间为100～125毫微秒。在100～125毫微秒频率编码期间,接收     

共面波导延迟线薄膜电路研制

基于薄膜电路工艺制作的共面波导延迟线不仅具有体积小、重量轻、损耗低、抗干扰性强等优点,还易与其他微波电路集成,延时精度较准。但它对高精度、密集孔薄膜电路的制作提出了更高的要求。通过优化薄膜电路制作工艺流程,研制出图形精度优于±5μm,具有良好金属化通孔的X波段两位延迟线薄膜电路。测试结果显示,该X波段两位延迟线的插入损耗为-5.7～-4.6 dB,带内起伏优于±0.3 dB,中心频率点相位偏差为±5°,满足设计要求。     

光纤频率传递光学相位补偿系统设计

设计了一种基于FPGA、温控光纤延迟线和压电陶瓷(PZT)光纤延迟线的光纤频率传递主动光学相位补偿系统,设计和制作了大动态范围温控光纤延迟线及其驱动电路。在基于Round-Trip方案的20km光纤频率传递实验系统中进行了测试。     

亮度延迟线的故障检修与代换

<正> 亮度延迟线用于彩色电视机的亮度通道,其作用是将亮度信号延迟0.5～0.7μs,使其与色度信号同时到达显像管,以避免出现色镶边现象。亮度延迟线的电路符号见图1。 亮度延迟线的种类 彩电中使用的亮度延迟线主要有集中参数型和分布参数型两种。集中参数型延迟线实际上是一     

中值滤波电路的设计

本文采用我国首创的ＤＹＬ集成线性“与或”门设计成的中值滤波电路，该电路具有结构简单、延时小等优点，可用于实时信号处理。     

A STUDY ON CONTROLLABLE ANALOG DELAY LINE

This paper presents an analog delay line devised under the principle of an inventionof this country,the DYL integrated linear“AND-OR”gate.The analog delay line is distinguishedfor its features:simple in circuit structure,speedy in transmission,and capable of controlling thequantity of delay in the circuit by digital quantity.     

宽带圆极化整流天线的研究与设计

针对空间微弱射频能量收集,提出了一种宽带圆极化整流天线,其主要由射频能量接收天线和多频整流电路构成.为了获得宽频带特性,接收天线的辐射贴片采用对数周期交叉偶极子.同时,两对交叉偶极子均由环形的90°相位延迟线连接,且相互正交,从而实现天线的圆极化特性.多频整流电路由两个单阶电压倍压整流电路并联而成,为了提高整流电路的性能和效率,引入了具有两个枝节的新型阻抗匹配电路.仿真结果表明:接收天线的阻抗带宽和3 dB轴比带宽分别为1 100 MHz和350 MHz;多频整流电路的功率灵敏度达到-35 dBm,最大RF-DC整体转换效率可达76.5%.在辐射强度为6.02 μT,负载电阻为700 Ω时,测得整流天线负载端的输出电压约为139 mV,因此该整流天线适用于低功率射频能量收集应用.     

CMOS wideband analogue delay stage

A new second-order all-pass filter with maximum achievable delay-bandwidth-product (DBW) is presented. The proposed circuit will be used as a wideband delay element in impulse radio ultra-wideband transceivers. Benefiting from a simple architecture, the proposed circuit achieves a 60 ps delay across a 10 GHz bandwidth, which is the largest delay ever reported over such a wide bandwidth. In addition, the most noticeable advantage of this delay circuit is the small variation of group delay across a wide frequency range, which means negligibly small phase distortion introduced by the circuit     

Analog Circuit Design Methodology in a Low Power RISC Microprocessor

There are various kinds of analog CMOS circuits in microprocessors. IOs, clock distribution circuits including PLL, memories are the main analog circuits. The circuit techniques to achieve low power dissipation combined with high performance in newest prototype chip in the Super H RISC engines are described. A TLB delay can be decreased by using a CAM with a differential amplifier to generate the match signal. The accelerator circuit also helps to speed up the TLB circuit, enabling single-cycle operation. A fabricated 96-mm² test chip with the super H architecture using 0.35-m four metal CMOS technology is capable of 167-MHz operation at 300 Dhrystone MIPS with 2.0-W power dissipation.     

An Analog Delay Circuit for On-Line Visual Confirmation of Discriminated Neuroelectric Signals

An analog delay circuit which utilizes an inexpensive commercially available analog shift register is described. The delay circuit when used in conjunction with a window discriminator will display "on-line" visual confirmation of single neural events from extracellular recordings containing more than one spike class. The delay can be changed to include the entire spike waveform by adjusting a potentiometer in the delay circuit.     

一种高精度大动态范围的距离模拟脉冲发生方法研究

现有的产生距离模拟脉冲的方法中,数字延时电路只能达到ns量级的精度,模拟延时电路的延时范围又不足够作为距离模拟脉冲的使用,为了实现高精度大动态范围的延时,来产生激光测距仪的距离模拟脉冲,在研究了现有方法的基础上,采用了数模结合的方案,设计了一种同时满足高精度和大动态范围的延时脉冲信号发生电路,并对其精度和重复性进行了测试,可以实现2 s～4 ms 的延时范围并具有0.1 ns的延时精度,即可以模拟300 m～600 km的距离并具有 1.5 cm的距离精度。解决了现有的距离模拟电路无法同时满足高精度、大动态范围的矛盾。     

Certified timing verification and the transition delay of a logiccircuit

Most research in timing verification has implicitly assumed a single vector floating mode computation of delay which is an approximation of the multivector transition delay. In this paper we examine the transition delay of a circuit and demonstrate that the transition delay of a circuit can differ from the floating delay of a circuit. We then provide a procedure for directly calculating the transition delay of a circuit. The most practical benefit of this procedure is the fact that it not only results in a delay calculation but outputs a vector sequence that may be timing simulated to certify static timing verification     

无源非线性延迟锁定保护电路的分析

本文提出一种简单的无源非线性延迟锁定保护电路，它除具有由复杂的数字逻辑电路构成的计数式延迟锁定保护电路的功能外，对实际工程上常用的ｒｃ低通电路相关处理情况，还优于后者。本文分析了无源非线性延迟锁定保护电路的性能，给出了理想积分和ｒｃ低通电路相关处理两种情况下的确定保持时间的均值和方差，奠定了这种保护系统的理论基础。     

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.