Easily Testable Cellular Carry Lookahead Adders

Cellular Carry Lookahead (CLA) adders are systematically implemented in arithmetic units due to their regular, well-balanced structure. In terms of testability and with respect to the classical Cell Fault Model (CFM), cellular CLA adders have poor testability by construction. Design-for-testability (DFT) modifications for cellular CLA adders have been proposed in the literature providing complete CFM testability making the adders either level-testable or C-testable. These designs impose significant area and performance overheads. In this paper, we propose DFT modifications for cellular CLA adders to achieve complete CFM testability with special emphasis on the minimum impact in terms of area and performance. Complete CFM testability is achieved without adding any extra inputs to the adder, with very small area and performance overheads, thus providing a practical solution. The proposed DFT scheme requires only 1 extra output and it is not necessary to put the circuit in a special test mode, while the earlier schemes require the addition of 2 extra inputs to set the circuit in test mode. A rigorous proof of the linear-testability of the adder is given and a sufficient linear-sized test set is provided that guarantees 100% CFM fault coverage. Surprisingly, the size of the proposed linear-sized test set is, in most practical cases, comparable or even smaller than a logarithmic-sized test set proposed in the literature.     

A synthesis-based test generation and compaction algorithm for multifaults

Because of its inherent complexity, the problem of automatic test pattern generation for multiple stuck-at faults (multifaults) has been largely ignored. Recently, the observation that multifault testability is retained by algebraic factorization demonstrated that single fault (and therefore multifault) vector sets for two-level circuits could give complete multifault coverage for multilevel circuits constructed by algebraic factorization. Unfortunately, in using this method the vector set size can be much larger than what is really required to achieve multifault coverage, and the approach has some limitations in its applicability.In this article we first present a multifault test generation and compaction strategy for algebraically factored multilevel circuits, synthesized from two-level representations. We give a basic sufficiency condition for multifault testability of such networks.We next focus on the relationship between hazard-free robust path-delay-fault testability and multifault testability. We show that the former implies the latter for arbitrary multilevel circuits. This allows the use of previously developed composition rules that maintain path-delay-fault testability for the synthesis of multifault testable circuits.We identify a class of multiplexor-based networks and prove an interesting property of such networks—if the networks are fully single stuck-at fault testable, or made fully single stuck-at fault testable, they are completely multifault testable. We give a multifault test generation and compaction algorithm for such networks.We provide experimental results which indicate that a compacted multifault test set derived using the above strategies can be significantly smaller than the test set derived using previously proposed procedures. These results also indicate the substantially wider applicability of our procedures, as compared to previous techniques.     

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS’85 and full-scan ISCAS’89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.     

Testability of parity checkers

Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed     

Reversed ROBDD circuits

A new class of logic circuits is proposed. Being derived from reduced ordered binary decision diagrams (ROBDD), these circuits inherit compactness and the ability to represent very large switching functions. The reversed signal propagation results in low dynamic power consumption, complete single stuck-at fault testability and fault security. Simulation results are presented     

A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.This revised version was published online in March 2005 with corrections to the cover date.     

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.     

Fault Diagnosis in Mixed-Signal Low Testability System

This paper describes a new approach for fault diagnosis of analog multi-phenomenon systems with low testability. The developed algorithms include identification of ambiguity groups, fault diagnosis methodology and solving low testability equations. Our aim is to identify a minimum number of faulty parameters that satisfy the test equations called a minimum form solution. An algorithm to find a minimum form solution is presented, which is based on the solution invariant matrix and an identification of singular cofactors of this matrix. System simulation using a developed C++ and Matlab programs was performed to test different faulty circuits. Test examples are discussed and simulation results are presented.     

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.     

Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits

Automatic test pattern generation (ATPG) remains one of themost complex CAD tasks. Therefore, numerous methods were proposed tospeed up ATPG by using parallelism. In this paper, we focus onparallelizing ATPG for stuck-at faults in sequential circuits bycombining fault and search space parallelism. Fault parallelism isapplied to so-called easy-to-detect faults. The main task of thisapproach is to find a best-suited partitioning of the fault list,based on dependencies between faults. For hard-to-detect faultsleft by fault parallelism, search space partitioning is applied,integrating depth-first and breadth-first search. Since a smalltest set size is mandatory for a cheap test and fault parallelismincreases the number of test patterns, test set compaction is donein a post-processing phase. Results show that our approach is notonly capable of achieving potentially superlinear speedups, but alsoimproves test set quality. The parallel environment we use consistsof a network of 100 workstations connected via ethernet.     

Fault characterization, testing considerations, and design fortestability of BiCMOS logic circuits

The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented     

An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits

Reversible logic has gained interest of researchers worldwide for its ultra-low power and high speed computing abilities in the future quantum information processing. Testing of these circuits is important for ensuring high reliability of their operation. In this work, we propose an ATPG algorithm for reversible circuits using an exact approach to generate CTS (Complete Test Set) which can detect single stuck-at faults, multiple stuck-at faults, repeated gate fault, partial and complete missing gate faults which are very useful logical fault models for reversible logic to model any physical defect. Proposed algorithm can be used to test a reversible circuit designed with k-CNOT, Peres and Fredkin gates. Through extensive experiments, we have validated our proposed algorithm for several benchmark circuits and other circuits with family of reversible gates. This algorithm produces a minimal and complete test set while reducing test generation time as compared to existing state-of-the-art algorithms. A testing tool is developed satisfying the purpose of generating all possible CTS’s indicating the simulation time, number of levels and gates in the circuit. This paper also contributes to the detection and removal of redundant faults for optimal test set generation.     

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.     

A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory,Design and Implementation

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. The Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems has been adopted for on-line detection of stuck-at faults in Digital Circuits. Efficient computational techniques to deal with very large state spaces based on Ordered Binary Decision Diagrams and Abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core. The tool can handle generic digital circuits with cell count as high as 15,000 and having the order of 2⁵⁰⁰ states. This is believed to be an improvement of an order of magnitude over results presented in the literature. This methodology enables the designer to tradeoff fault coverage and detection latency against area and power overhead. The design flow using the CAD tool developed is described and results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The methodology is further validated by design, fabrication, and testing of an ASIC in 0.18 μ technology.     

Theorems for Fault Collapsing in Combinational Circuits

This paper gives a mathematical approach to fault collapsing based on the stuck-at fault model for combinational circuits. The mathematical structure we work within is a Boolean ring of Boolean functions of several variables. The goal of fault collapsing for a given circuit is to reduce the number of stuck-at faults to be considered in test generation and fault diagnosis. For this purpose we need rules that let us eliminate faults from the considered fault set. In this paper some earlier known rules are proved in the new context, and several new rules are presented and proved. The most important of the new theorems deal with the relationship between stuck-at faults on a fanout stem and the branches. The concept of monotony of Boolean functions appears to be important in most of these new rules. Editor: M. Hsiao Audhild Vaaje received the M.S. degree and the Ph.D. degree in mathematics from University of Oslo in 1971 and 1992, respectively. She is an associate professor of mathematics at Agder University College in Norway, where she has been employed since 1972. She has research interests in mathematics applied to fault detection in digital circuits.     

基于故障插入的电路抗老化输入矢量生成研究

随着CMOS工艺特征尺寸的不断缩小,晶体管的老化效应严重影响了电路的可靠性,负偏置温度不稳定性(NBTI)是造成晶体管老化的主要因素之一。提出了一种基于固定故障插入的电路抗老化输入矢量生成方法,在电路的合适位置插入固定故障,通过自动测试向量生成(ATPG)工具获取较小的备选抗老化矢量集合,再从中筛选出最优矢量。由该方法生成的输入矢量可以使电路在待机模式下处于最大老化恢复状态,同时具有较小的时间开销。在ISCAS85电路中的仿真结果表明,与随机矢量生成方法相比,在电路待机模式下加载本文方法生成的输入矢量,可以达到最高17%的电路老化时延改善率。     

Symbolic Techniques for the Selection of Test Frequencies in Analog Fault Diagnosis

In this work symbolic methods are used for implementing a procedure for the selection of test frequencies in multifrequency parametric fault diagnosis of analog linear circuits. The proposed approach is based on the evaluation of the condition number and the norm of a sensitivity matrix of the circuit under test. This matrix is determined by exploiting the testability and ambiguity group concepts. A Test Error Index (T.E.I.) is obtained which permits to select the set of frequencies which better leads to locate parametric faults in analog linear circuits. A program implementing the proposed procedure has been realized by using symbolic techniques. Examples of application are also included.