一种用于cdna2000的新的Turbo码迭代译码方案

由于Ｔｕｒｂｏ码优异的纠错性能使得其在第三代移动通信（３Ｇ）系统中倍受重视。无论是ＷＣＤＭＡ还是ｃｄｍａ２０００都将其作为侯选的信道编码方案，并且将其列为３Ｇ的核心技术之一。本文将ｃｄｍａ２０００中的Ｔｕｒｂｏ码和同等译码复杂度的卷积码进行比较，给出了在加性白高斯噪声信道和瑞利衰落信道中的仿真结果。     

一种性能优越的Turbo码SOVA译码算法

MAP译码算法性能上是最优的,但是其复杂度也是十分高的,影响了硬件的实现,介绍了一种性能上接近于MAP译码算法,复杂度上有明显减少的译码算法,并且对其进行了完善,仿真结果表明对于二进制Turbo码,改进后的译码算法与MAP算法的译码性能更为接近。     

Turbo码的编译码器及性能分析

介绍Turbo码的编译码器和迭代译码器的结构 ,并分析Turbo的性能     

不同译码器结构对Turbo码性能的影响

文章给出了两种译码顺序不同的Ｔｕｒｂｏ码译码器,并通过软判决维特比算法作译码业比较两种结构的译码效果。     

一种用于无线ATM的Turbo码的研究

无线ATM能通过标准的ATM网络应用接口,为多种移动终端提供综合宽带业务的传输和交换。研究了适用于无线ATM的Turbo码,对Turbo码与卷积码的性能进行了比较,并且对不同编码效率下Turbo码的纠错能力进行了仿真研究。     

WCDMA与cdma2000的Turbo码交织器性能比较

对一种Turbo码交织器性能分析的方法进行了讨论,用这种方法分析比较了WCDMA和cdma2000中Turbo码交织器的性能,并给出迭代译码的计算机仿真结果,以证实这种方法的正确性.此外,仿真结果还证实文献[3]中的评价交织器的方法不一定适合Turbo码交织器.     

卷积Turbo码技术研究

系统地研究了卷积Turbo码的编译码结构和两种译码算法,分析了影响译码性能的几个因素,并给出了相应的仿真结果。     

一种基于FPGA的Turbo码译码器的设计

主要论述了一种基于FPGA的Turbo码译码器的设计。首先简单介绍了编码器和交织器的原理;然后介绍了基于Max-Log-MAP算法的译码器原理,详细论述了各个子模块;最后给出了系统仿真的误码率图形。     

不同译码器结构对Turbo码性能的影响

本文给出了两种译码顺序不同的Ｔｕｒｂｏ码译器，并通过软判决维持比算法作译码来比较两种结构的译码效果。     

部分系统Turbo码的研究

对一种码率为1／2的部分系统turbo码性能进行了讨论。它是通过对码率为1／3的turbo码的校验位和信息位进行删余得到的。这种码的“误码下限”（error-floor）比对应的系统码要低。因此,码率为1／2的turbo码,在没有增加编码和译码复杂性的情况下,通过简单地对信息位和校验位的删除可以提高性能。     

一种基于QC-LDPC码的低复杂度分层迭代译码器

针对具有准循环结构的LDPC码,设计了一种低复杂度译码器。利用校验矩阵的循环特性以及分层迭代的译码算法,对一般的分层迭代架构进行改进,实现了译码器流水线处理,有效的减少迭代时间,提高吞吐量,最后针对码长为1200的LDPC码,基于FPGA平台Kintex7 xc7k325的芯片实现了该架构设计,结果表明,该译码器只消耗了100多个Slices和几块RAM,有效节省了硬件资源,同时译码时间比一般的分层架构减少了2/3左右,吞吐量提高了约2倍,研究成果具有重要的实用价值,可应用于资源有限的低速通信领域。     

A Hybrid Decoder for Block Turbo Codes

We propose a novel iterative decoder for block turbo codes (BTCs). The proposed decoder combines soft-input/softoutput (SISO) and hard-input/hard-output (HIHO) constituent decoders in order to obtain better error performance and reduce the computational complexity compared to classical BTC decoders. We show that the new decoder, called ?hybrid decoder?, offers a better complexity/performance tradeoff than a classical BTC decoder.     

A Simple Efficient Stopping Criterion for Turbo Decoder

The performance of a turbo decoder depends strongly on the number of iterations in its decoding process. It is necessary to stop the decoding process at an appropriate moment to alleviate the serious burden, in terms of both the computational speed and latency, part of which is associated with too many iterations. In this letter, we introduce a criterion for finding the opportune moment to stop the decoding process, called a hard decision aided criterion based on bit interleaved parity, which is known to have much simpler hardware logic, compared with other schemes, and does not lead to any significant performance degradation.     

Very Low-Complexity Hardware Interleaver for Turbo Decoding

This brief presents a very low complexity hardware interleaver implementation for turbo code in wideband CDMA (W-CDMA) systems. Algorithmic transformations are extensively exploited to reduce the computation complexity and latency. Novel VLSI architectures are developed. The hardware implementation results show that an entire turbo interleave pattern generation unit consumes only 4 k gates, which is an order of magnitude smaller than conventional designs.     

A Flexible UMTS-WiMax Turbo Decoder Architecture

This work proposes a VLSI decoding architecture for concatenated convolutional codes. The novelty of this architecture is twofold: 1) the possibility to switch on-the-fly from the universal mobile telecommunication system turbo decoder to the WiMax duo-binary turbo decoder with a limited resources overhead compared to a single-mode WiMax architecture; and 2) the design of a parallel, collision free WiMax decoder architecture. Compared to two single-mode solutions, the proposed architecture achieves a complexity reduction of 17.1% and 27.3% in terms of logic and memory, respectively. The proposed, flexible architecture has been characterized in terms of performance and complexity on a 0.13-mum standard cell technology, and sustains a maximum throughput of more than 70 Mb/s.     

Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes

This paper studies low-complexity high-speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path. Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. Based on the proposed architectures, a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex-II 6000, where an efficient nonuniform quantization scheme is employed to reduce the size of memories storing soft messages. FPGA implementation results show that the proposed decoder can achieve a maximum (source data) decoding throughput of 172 Mb/s at 15 iterations     

cdma2000系统中导频干扰抵消方案研究

本文介绍了cdma2000系统中计算和消除导频信号干扰的一种有效方法,并将其应用于单个和多个蜂窝小区的环境中.仿真结果表明,采用本方法的RAKE接收机既可以保证信道估计的精度,合并接收到的多径信号;又可以有效地消除由导频信号所引入的多址干扰,使得系统性能得到较大程度的提高.同时,符号速率上的导频干扰抵消运算大大降低了实际系统中硬件实现时的复杂度.     

Low-Complexity High-Rate Reed--Solomon Block Turbo Codes

This letter considers high-rate block turbo codes (BTC) obtained by concatenation of two single-error-correcting Reed-Solomon (RS) constituent codes. Simulation results show that these codes perform within 1 dB of the theoretical limit for binary transmission over additive white Gaussian noise with a low-complexity decoder. A comparison with Bose-Chaudhuri-Hocquenghem BTCs of similar code rate reveals that RS BTCs have interesting advantages in terms of memory size and decoder complexity for very-high-data-rate decoding architectures.