基于FCM的芯粒测试电路设计与实现

设计了一种改进的2.5D芯粒可测性电路，电路的核心是位于中介层的灵活可配置模块（Flexible configu?rable modules,FCM），该模块基于IEEE 1838标准提出的灵活并行端口设计，采用双路斜对称设计结构，水平方向的两条线路可同时向左和向右传输控制信号以及测试数据，彼此独立互不干扰。与IEEE 1838灵活并行端口相比，FCM可以简化扫描测试配置步骤，满足水平双线路传输场景需求。仿真结果表明，基于FCM设计的2.5D芯粒测试电路可以实现对原有可测性设计（Design for test,DFT）测试逻辑的复用，满足芯粒即插即用的策略，提升测试的灵活性和可控性。     

基于VXI总线的通用接口模块设计

通过对VXI总线接口工作原理的深入分析，采用大规模可编程逻辑器件，设计了一种基于VXI总线A16／D16寄存器基的通用接口电路，实现了将复杂的VXI总线协议的应用转换为对简单的端口访问。采用通用的定点DSP器件和SPI总线技术，完成对VXI消息的解析和本地模块的电路控制。根据本文设计的通用接口模块已经在多个项目中得到应用，具有集成度高、适应性好等优点。     

同步突发静态RAM(SBSRAM)及其在DSP系统中的应用

介绍同步突发静态RAM的特点及结构，并就其与DSP(digital signal processor)的接口信号、控制寄存器、读写操作、时序设计，数据访问时的等待状态等进行讨论。最后给出一个SBSRAM在信号处理系统中的应用实例。     

基于外壳架构与测试访问机制的数字芯核可测试性设计

深亚徽米技术的应用以及芯核的嵌入性特点.使传统的测试方法不再能满足芯核测试的需要.IEEEStdl 500针对此问题提出了芯核的可测试性设计方案——外壳架构和测试访问机制.基于IEEE Stdl 500.以74373与741 38软梭为例,提出数字芯梭可测试性设计的方法,并通过多种指令仿真验证了设计的合理性;设计的TAM控制器复用JTAC-端口,节约了测试端口资源.提供了测试效率.     

双压电膜驱动微小机器人控制器的研究

设计了一种适用于双压电膜驱动的微小型机器人控制器.控制器主要由信号发生电路及高压放大电路组成.信号发生电路采用直接数字信号合成器(DDS)技术及静态随机存储器(SRAM)内存查表技术,利用硬件描述语言(VHDL)和原理图描述方法对现场可编程门阵列器件(FPGA)进行设计,产生的信号通过集成功率运算放大器对机器人进行驱动控制.最后进行了控制器性能测试,完成了该控制器样机的试验.     

一种基于BGA技术的X波段射频接口设计（英文）

文中设计了一种高隔离度、低插损的小型化射频接口技术。该射频接口工作于X波段，采用球栅阵列(BGA)技术代替传统的电连接器作为射频模块的对外接口，通过电路基板内部的传输路径及垂直过渡将射频模块内部的信号传输至接口。对该接口技术的可行性进行了分析，通过仿真计算确定了接口电路的关键参数，并设计了测试夹具，对该接口技术的射频性能进行了测试。测试结果表明，在8 GHz～12 GHz的频率范围内，该射频接口技术的驻波小于1.2,插入损耗小于0.1 dB,端口间的隔离度小于-80 dB。根据此结构设计了一款X波段TR组件并加工试验件进行测试，测试结果满足设计要求。     

Port Scale RF测试解决方案

V93000 SoC测试平台提供可靠的RF测量能力,可以对整合射频、混合信号、数字、电源管理、嵌入式或堆叠式内存的各类最新的高集成度芯片进行测量。PortScale射频测试解决方案的设计采用固态设计,RF资源都集中在测试头中。PortScaleRFSE具配置12、24或48个射频测试端口。     

基于边界扫描技术的Flash测试技术研究

提出了一种片内存储器的可测性设计方法.在详细分析了边界扫描技术的结构,功能与控制原理的基础上:设计了一种存储器测试接口.该接口符合JTAG标准(IEEE 1149.1标准),其中包含了标准的指令寄存器设计,用来控制访问不同的扫描链.在权衡了测试效率和芯片面积的基础上,提出了一种在线测试器电路的设计方法.实验表明,该测试电路可以以小的面积开销而节省大量测试时间.     

用MACH465完成PCI总线接口设计

该设计提供了一个PCI总线上简单的主从接口设计.主接口能支持突发方式.1.在适配卡上由MACH465提供PCI总线与本地总线的接口.2.数据缓冲器由其他电路完成3.配置寄存器由其他电路完成该设计所具备的基本功能有:1.读写控制2.访问存储器和I/O空间3.信号均衡产生和检测4.对目标中断和回复的反应5.主机中止处理     

PCI功能软接口快速设计

主要介绍了PCI功能的软接口设计。首先讲述PCI功能的配置空间、配置首部格式，以及如何快速获得PCI功能的配置空间内容，从而获得PCI功能寄存器基址，由此访问PCI功能寄存器，进行PCI功能软接口设计。     

Secure JTAG Implementation Using Schnorr Protocol

The standard IEEE 1149.1 (Test Access Port and Boundary-Scan Architecture, also known as JTAG port) provides a useful interface for embedded systems development, debug, and test. In an 1149.1-compatible integrated circuit, the JTAG port allows the circuit to be easily accessed from the external world, and even to control and observe the internal scan chains of the circuit. However, the JTAG port can be also exploited by attackers to mount several cryptographic attacks. In this paper we propose a novel architecture that implements a secure JTAG interface. Our JTAG scheme allows for mutual authentication between the device and the tester. In contrast to previous work, our scheme uses provably secure asymmetric-key based authentication and verification protocols. The complete scheme is implemented in hardware and integrated with the standard JTAG interface. Detailed area and timing results are also presented.     

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch

The present paper introduces a new strategy for testing embedded cores using Test Access Mechanism (TAM) switches. An algorithm has been proposed for testing the cores using the TAM switch architecture. In addition, a scheme for testing the interconnections between cores in parallel is also presented. Experiments have been carried out on several synthetic SOC benchmarks. Results show significant optimization of area overhead as well as test time.     

Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip

Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips since most mainstream memories use a source-synchronous interface. This paper presents a new Skew Measurement and Compensation Module (SMCM) design for off-chip skew calibration from Time Domain Reflectometry (TDR) measurements. It consists of coarse and fine parts which enable the circuit to detect a large skew range with high resolution. Circuit complexity is reduced through use of the proposed automatic edge detection method which controls coarse/fine operations. We also present skew compensation circuits which can de-skew off-chip signals based on the skew calibration. The SMCM occupies a small area, making it suitable for implementation in a Built-Off Test (BOT) chip. The circuits were implemented using a 130 nm technology in a Built-Off Test Interface (BOTI) developed for 800 Mbps DDR2 memory functional test.     

边界扫描测试技术的原理及其应用

边界扫描技术是一种应用于数字集成电路器件的标准化可测试性设计方法，他提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案，极大地方便了系统电路的测试。自从1990年2月JTAG与TEEE标准化委员会合作提出了“标准测试访问通道与边界扫描结构”的IEEE1149．1—1990标准以后，边界扫描技术得到了迅速发展和应用。利用这种技术，不仅能测试集成电路芯片输入／输出管脚的状态，而且能够测试芯片内部工作情况以及直至引线级的断路和短路故障。对芯片管脚的测试可以提供100％的故障覆盖率，且能实现高精度的故障定位。同时，大大减少了产品的测试时间，缩短了产品的设计和开发周期。边界扫描技术克服了传统针床测试技术的缺点，而且测试费用也相对较低。这在可靠性要求高、排除故障要求时间短的场合非常适用。特别是在武器装备的系统内置测试和维护测试中具有很好的应用前景。本文介绍了边界扫描技术的含义、原理、结构，讨论了边界扫描技术的具体应用。     

A New Phase-Locked Oscillator Adaptable to Input Signals with Periodical Phase Jumps

A new polyphase phase-locked oscillator (P-PLO) is proposed which overcomes one of the greatest difficulties in the passive bus configuration: timing extraction from signals in multiplexed channels with different mean phases. The proposed oscillator generates appropriate retiming clock pulses for each channel independent of other channels. Moreover, since pulse overlaps between channels may appear at the first and last bits of each channel, the oscillator shifts retiming clock phases of these bits to avoid sampling overlaps. A performance analysis method extended from the conventional Markov chain model is also proposed. The theoretically obtained jitter and retiming margin characteristics correspond closely to experimental results. This circuit is also shown to be adaptable to point-to-point configurations which, like passive bus, will be used in the ISDN basic interface recommended as one of the 1-series interfaces by CCITT. This allows easy rearrangement of interface wiring, e.g., changing from the passive bus to point-to-point configuration, without any adjustment of the network terminator.     

"龙腾"S2微处理器测试结构设计

介绍了"龙腾"52微处理器测试结构设计方法,详细讨论了采用全扫描测试、内建自测试(BIST)等可测性设计(DFT)技术.该处理器与PC104全兼容,设计中的所有寄存器采用全扫描结构,设计中的存储器采用内建自测试,整个设计使用JTAG作为测试接口.通过这些可测性设计,使芯片的故障覆盖率达到了100%,能够满足流片后测试需求.     

支持多处理器通信的同/异步串口的设计

同/异步串口集成了同步和异步串口的功能,相比于单一功能的串口,配置灵活,且节约芯片资源。通过模块化设计方法实现同/异步串口的设计与仿真,并着重在内部模块设计中体现同步和异步功能的有效结合,合理复用逻辑功能。利用寄存器实现模块同异步功能及参数的可配置性,设计实现了9位唤醒模式,以支持多处理器通信。逻辑综合的结果显示,该串口具有良好的性能。目前,该串口已应用于高端32位DSP,工作稳定。     

一种基于0.35 μm CMOS工艺的单片集成微机械陀螺仪接口电路

本文介绍了一种用于读取角速度信号的单片集成微机械陀螺仪接口电路,该接口电路采用了相关双采样技术以抑制1/f噪声和运算跨导放大器的失调.为了方便系统仿真和测试,本文设计了一种微机械陀螺仪的等效电路.该接口电路采用0.35 μm CMOS工艺设计并制造,芯片总面积为1.09mm×0.87mm.后仿真结果表明,该接口电路能达到0.58aF的电容分辨精度,动态范围达99.7dB.测试结果表明,接口电路系统增益为26.6mV/fF,在3.5V电源电压下系统总功耗为20.4mW.     

An on-chip march pattern generator for testing embedded memorycores

In this correspondence, we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data within the steps of the algorithms. Therefore, the proposed pattern generator is capable of generating any march algorithm with small area overhead